Hardware Software Partitioning Using Immune Algorithm Based on Pareto

Liu, Yang; Li, Qing Cheng

doi:10.1109/aici.2009.39

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…Liu et al use improved directed acyclic graph to model the HW/SW partitioning problem, and subsequently make use of the immune algorithm to solve it [12]. Further-more, concerning the multi-objective optimization on HW/SW partitioning problem, they propose an immune algorithm to obtain the parieto optimal solution [13].…”

Section: Related Workmentioning

confidence: 99%

Shuffled Frog Leaping Algorithm for Hardware/Software Partitioning

Du¹,

Kong²,

Zuo³

et al. 2014

JCP

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Reconfigurable system on chip is well known for its flexibility for high performance embedded systems. The hardware/software (HW/SW) partitioning is the most important phase during the design of reconfigurable system on chip. A great many different algorithms have been adopted for solving the hardware/software partitioning problem. Shuffled Frog Leaping Algorithm (SFLA) is popular for its simple concepts, little parameter adjustment, high calculation speed, strong global search optimization capability and easy execution. In this paper, we apply the SFLA algorithm to solving hardware/software partitioning problem on reconfigurable system on chip with coarsegrained. The experimental results show that the SFLA algorithm can reduce the time cost by 45.54% on average with three different area constrain, compared with greedy algorithm. The time cost of SFLA algorithm are also reduced by 23.57% and 9.99% on average with simulated annealing algorithm (SA) and combined algorithm with greedy and simulated annealing algorithm (GSA). When area constrain is a half of area cost which all tasks are implemented by hardware will be taken, SFLA algorithm can reduce the time cost by 51.30%, 21.04% and 11.61% on average, compared with that of Greedy algorithm, SA, and GSA, respectively.

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Section: Related Workmentioning

confidence: 99%

Shuffled Frog Leaping Algorithm for Hardware/Software Partitioning

Du¹,

Kong²,

Zuo³

et al. 2014

JCP

View full text Add to dashboard Cite

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Hardware software partitioning of crankshaft function in engine control units using FPGA-based testing

Chein

Fariq

Rahman

et al. 2017

2017 IEEE 15th Student Conference on Research and Development (SCOReD)

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The automotive industry shows a gradual transition from a simple transportation model to a car that relies on electronics for safety control. A modern car will offer many features in which the car drive or park automatically; this shows the effort of the automotive industry in increasing the consumer's safety level on the road. The increasing awareness of safety results in reliance of today cars on the electronic controlling components such as engine, steering, transmission, braking system and airbags. This project proposes hardware and software codesign that provides flexibility, timing precision, performance, manageable software design, complexity and meets safety requirement. The solution is aligned with Application-Specific Integrated Circuit (ASIC), which features complex control algorithm, implementation in hardware and controllable through firmware.

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Hardware Software Partitioning Using Immune Algorithm Based on Pareto

Cited by 2 publications

References 9 publications

Shuffled Frog Leaping Algorithm for Hardware/Software Partitioning

Shuffled Frog Leaping Algorithm for Hardware/Software Partitioning

Hardware software partitioning of crankshaft function in engine control units using FPGA-based testing

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