Hardware spiking neural network prototyping and application

Cawley, Seamus; Morgan, Frank; McGinley, Brian; Pande, Sandeep; McDaid, Liam; Carrillo, Snaider; Harkin, Jim

doi:10.1007/s10710-011-9130-9

Cited by 46 publications

(22 citation statements)

References 33 publications

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“…Various approaches have been explored for SNN implementation, including software, application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) [7]. The software approaches are too slow for the large-scale SNNs simulation and have limited scalability due to the huge power consumption [8].…”

Section: Background and Related Workmentioning

confidence: 99%

An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

Luo

Wan

Liu

et al. 2018

Neural Process Lett

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The basic processing units in brain are neurons and synapses that are interconnected in a complex pattern and show many surprised information processing capabilities. The researchers attempt to mimic this efficiency and build artificial neural systems in hardware device to emulate the key information processing principles of the brain. However, the neural network hardware system has a challenge of interconnecting neurons and synapses efficiently. An efficient, low-cost routing architecture (ELRA) is proposed in this paper to provide a communication infrastructure for the hardware spiking neuron networks (SNN). A dynamic traffic arbitration strategy is employed in ELRA, where the traffic status weights of input ports are calculated in real-time according to the channel traffic statuses and the port with the largest traffic status weight is given a high priority to forward packets. This strategy enables the router to serve congested ports preferentially, which can balance the overall network traffic loads. Experimental results show the feasibility of ELRA under various traffic scenarios, and the hardware synthesis result using SAED 90nm technology demonstrates it has a low hardware area overhead which maintains scalability for large-scale SNN hardware implementations. Recently, researchers proposed the networks-on-chip (NoC) interconnect paradigm [1,[4][5][6] as a promising solution to solve the inter-neuron connectivity problems and achieved a satisfactory performance [1,4]. The NoC is similar to the computer network where the processing elements (e.g. neurons in the SNN) are connected by the routers and channels [6]. For the SNN, the spikes are packetized and can be forwarded from any source node to any destination node; thus the information exchange between the neurons is established. In general, a group of neurons (e.g.∼ten in the approach of Carrillo et al. [4]) are connected to one router, but the required routers and channels increase if the number of neurons increases, which leads to the hardware area and power dissipation consumption. Thus the NoC architecture (i.e. routers and channels) constraints the system scalability [1], and it should achieve a trade-off between performance (e.g. spike throughput and communication delay etc.) and resource consumption (e.g. hardware area and power consumption). Performance: the NoC routers are responsible for transmitting highly irregular spike events. An effective router should forward as many spike events as possible in a short time period for various traffic scenarios, i.e. to provide high throughput for the communications. In addition, the irregular spike patterns occasionally introduce traffic congestions [4], which require the router have the ability to monitor the different traffic status (e.g. busy or congested etc.) and deal with various traffic patterns [5]. Resource consumption: the number of required routers increases proportionally with the number of neurons and synapses [1]. A low-cost routing architecture is very crucial for large-scale SNN hardware sys...

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Section: Background and Related Workmentioning

confidence: 99%

An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

Luo

Wan

Liu

et al. 2018

Neural Process Lett

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“…To address the scalability issue, there are works adopt NoC technique with SNN. EMBRACE is an FPGA based flexible and reconfigurable SNN architecture [19]. It uses NoC to handle inter-neuron communication.…”

Section: Related Workmentioning

confidence: 99%

Scalable NoC-based Neuromorphic Hardware Learning and Inference

Fang

Shrestha

et al. 2018

2018 International Joint Conference on Neural Networks (IJCNN)

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Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timingdependent plasticity (STDP) mechanism for learning. Existing hardware implementations of SNN are limited in scale or do not have in-hardware learning capability. In this work, we propose a low-cost scalable Network-on-Chip (NoC) based SNN hardware architecture with fully distributed in-hardware STDP learning capability. All hardware neurons work in parallel and communicate through the NoC. This enables chip-level interconnection, scalability and reconfigurability necessary for deploying different applications. The hardware is applied to learn MNIST digits as an evaluation of its learning capability. We explore the design space to study the trade-offs between speed, area and energy. How to use this procedure to find optimal architecture configuration is also discussed.

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“…The authors have investigated and proposed EMBRACE (figure 1), a NoC based hardware SNN architecture for implementation of large scale SNNs, specifically targeted at embedded applications [10] [11]. A Modular Neural Tile (MNT) architecture has been proposed for reducing the silicon area, by using a combination of fixed and configurable synaptic connections [12].…”

Section: Noc Architectures For Hardware Snnsmentioning

confidence: 99%

Fixed latency on-chip interconnect for hardware spiking neural network architectures

Pande¹,

Morgan²,

Smit³

et al. 2013

Parallel Computing

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Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable operation of SNN applications. A packet switched Network on Chip (NoC) infrastructure offers scalable connectivity for spike communication in hardware SNN architectures. However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency. This packet latency jitter alters spike timings and distorts the information conveyed on the synaptic connections in the SNN, resulting in unreliable application behaviour. This paper presents a simulation-based analysis of this synaptic information distortion in NoC based hardware SNNs.The paper proposes a ring topology interconnect for spike communication between neural tiles, and a timestamped spike broadcast flow control scheme that offers fixed spike transfer latency. The proposed architectural technique is evaluated using spike rates employed in previously reported hardware SNN applications. Results indicate that the proposed interconnect offers fixed spike transfer latency and eliminates the associated information distortion.The paper presents the micro-architecture of the proposed ring router. The ring interconnect architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65nm low-power CMOS technology. Silicon area comparisons for various ring sizes are presented. Limitations on the scalability of the proposed ring architecture and selection of the optimal ring size based on spike rate resolution and hardware resources are discussed. A hierarchical, mesh topology NoC architecture with a 4 × 8 modular neural elements supporting 896 neurons and 72K synapses on a Xilinx Virtex-6 XC6VLX240T FPGA device is presented.

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Hardware spiking neural network prototyping and application

Cited by 46 publications

References 33 publications

An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations

Scalable NoC-based Neuromorphic Hardware Learning and Inference

Fixed latency on-chip interconnect for hardware spiking neural network architectures

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