Hardware Trojan horse detection using gate-level characterization

Abstract

Hardware Trojan horses (HTHs) are the malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. There are numerous HTHs sources including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. HTH attacks can greatly comprise security and privacy of hardware users either directly or through interaction with pertinent systems and application software or with data. However, while there has been a huge research and development effort for detecting software Trojan horses, surprisingly, HTHs are rarely addressed. HTH detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability.Our goal is to provide an impetus for HTH research by creating a generic and easily applicable set of techniques and tools for HTH detection. We start by introducing a technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay, which utilizes linear programming to solve a system of equations created using non-destructive measurements of power or delays. This technique is combined with constraint manipulation techniques to detect embedded HTHs. The effectiveness of the approach is demonstrated on a number of standard benchmarks.

Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry

“…It also easily explains the discrepancy of any global measurement as a consequence of the embedded HT. Recently, a significant progress has been made in the field of HT detection using gate-level characterization techniques where a large set of global measurements is used to calculate variation-dependent characteristics of each gate post-silicon [14,17,18,19,20,22]. Therefore, the variability aspects of PV are now addressed well.…”

A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection

“…Li and Lach propose adding on chip delay test structures for Trojan detection [27]. Gate-level characterization was used for postsilicon profiling [28]- [30] and its use for IC Trojan detection was first proposed in [9], [31] and also used in [10]- [13], [32], [33]. However, optimality guarantees (bounds), calibration, sensitivity, and multimodal combining were not discussed in the literature.…”

“…Using the timing signal signature by testing multiple path signatures was suggested [8]. Gate level characterization for Trojan detection was proposed [9]- [13] but no systematic formal analysis or optimal algorithms were discussed. The available methods are either based on ad-hoc measurements, heuristics for detection, calibration and test, or they use costly and slow destructive tests.…”

A Unified Submodular Framework for Multimodal IC Trojan Detection

“…Li and Lach propose adding on chip delay test structures for Trojan detection [16]. Gate level characterization for noninvasive post-silicon IC profiling [12] and for Trojan detection was used in [20,22,2,28]. However, the previous work did not provide a systematic algorithm with any kind of optimality, nor they addressed calibration, sensitivity, or multimodal combining.…”