Hardware Trojans: current challenges and approaches

Abstract

More and more manufacturers outsource parts of the design and fabrication of integrated circuits (ICs) for cost reduction. Recent publications show that such outsourcing can pose serious threats to governments and corporations, as they lose control of the development process. Until now, the threat of hardware Trojans is mostly considered during fabrication. Third party intellectual properties (IPs) are also gaining importance as companies wish to reduce costs and shorten the timeto-market. Through this study, the authors argue that the threat of Trojans is spread throughout the whole IC development chain. They give a survey of both hardware Trojan insertion possibilities and detection techniques. Furthermore, they identify the key vulnerabilities at each stage of IC development and describe costs of hardware Trojan insertion and detection. This way, the threat level based on feasibility of Trojan insertion and the practicability of Trojan detection techniques is evaluated. Lately, detection techniques address the issue of including third party IP. However, those techniques are not sufficient and need more research to effectively protect the design. In this way, the authors' analysis provides a solid base to identify the issues during IC development, which should be addressed with higher priority by all entities involved in the IC development.

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead

“…Besides, HTs inserted in unreliable foundries were the first threat to be studied extensively; it was more recently considered that the threat might as well come from the design phase where a HT can be introduced by a rogue designer or through an IP from third party providers [5,[79][80][81][82].…”

Towards Scalability Trade-off and Security Issues in State-of-the-art Blockchain

“…These are also designed to disclose the transaction secret information, Denial-of-Service, and alter the system functionality. Attackers can insert HTs at any level from the high-level system design specification to the transistor level of IC design flow [11]. A typical structure of HTs that could be inserted into Blockchain is shown in Figure 4.…”

Symbolic execution based test-patterns generation algorithm for hardware Trojan detection

“…The detection difficulty is highest at this stage because of prohibitive time and cost requirements ( Jacob et al, 2014 ). Current detection techniques mostly focus on post-fabrication stages and use a golden chip as a reference model.…”

“…The detection difficulty at the gate-level is medium ( Jacob et al, 2014 ) because the netlist is used to produce IC chips. Compared with chips, gate-level netlists provide more design information.…”