Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies

Rai, Shubham; Rupani, Ansh; Nath, Pallab Kumar; Kumar, Akash

doi:10.1109/isvlsi.2019.00123

Cited by 25 publications

(14 citation statements)

References 26 publications

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“…To this end, one RFET is operated in n‐mode (pull‐down transistor) by applying V PG = 3 V, whereas the pull‐up transistor is operated in p‐mode with V PG = −3 V. This reveals one of the key advantages of RFETs, which is the capability to use the exact same device layout that is, geometry and composition for both n‐ and p‐type operation, enabling a vast variety of applications such as functional diverse adaptive computing and hardware secure circuits. [ 24,27,67 ] Demonstrating this fundamental logic gate, the proposed Al‐Si NW RFET architecture proofs the applicability of the Al‐Si RFET platform to be implemented in complementary logic gates. Figure shows the realized complementary inverter based on the presented Al‐Si RFET device.…”

Section: Resultsmentioning

confidence: 74%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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Section: Resultsmentioning

confidence: 74%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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show abstract

“…Copyright infringements and illegal ownership claims on an IP have rapidly proliferated into a major security crisis for the semiconductor industry [ 123 ] with reported average annual losses of billions of dollars. [ 124 ] Therefore, claiming the rightful ownership of an IP in the court of law has garnered tremendous attention today.…”

Section: D‐material‐based Watermarking and Anticounterfeitsmentioning

confidence: 99%

“…[118] Copyright 2020, Springer Nature. the semiconductor industry [123] with reported average annual losses of billions of dollars. [124] Therefore, claiming the rightful ownership of an IP in the court of law has garnered tremendous attention today.…”

Section: D-material-based Watermarking and Anticounterfeitsmentioning

confidence: 99%

“…There have been several works on watermarking; [125][126][127][128][129] however, they deal with adding algorithmic constraints at various logic or physical synthesis levels. While recent developments in emerging technologies such as silicon and germanium nanowire reconfigurable FETs [123,[130][131][132] are promising, they are marred by area and energy overheads.…”

Section: D-material-based Watermarking and Anticounterfeitsmentioning

confidence: 99%

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Hardware and Information Security Primitives Based on 2D Materials and Devices

Wali

Das

2023

Advanced Materials

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Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon‐based complementary metal‐oxide‐semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon‐based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D‐materials‐based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large‐scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

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“…Hence, RFETs-based inverters present polymorphism from an altogether different angle, where the functionality remains the same but structurally they are different. Such multiple variants of the same logic gate can be used in watermarking schemes [73] or camouflaging techniques [74].…”

Section: The Curious Case Of Rfet-based Invertersmentioning

confidence: 99%

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Rai

Garg

Pilato

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from systemlevel down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.1 Not requiring any changes to the EDA flows.

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Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies

Cited by 25 publications

References 26 publications

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Hardware and Information Security Primitives Based on 2D Materials and Devices

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

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