HARE: Hardware accelerator for regular expressions

Gogte, Vaibhav; Kolli, Aasheesh; Cafarella, Michael; D’Antoni, Loris; Wenisch, Thomas F.

doi:10.1109/micro.2016.7783747

Cited by 43 publications

(12 citation statements)

References 24 publications

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“…Accelerator designs have been proposed for query procssing bottlenecks [11,28,35,38,41,50,55,56]. Researchers have explored customized accelerators for common operators in SQL such as join [56], partition [11,55,56], sort [56], aggregation [56], regex search [28,50,56], and index traversal [38]. Deploying an accelerator for each task is challenging -design and deployment cost, and obsolescence when new algorithms emerge.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Accelerating raw data analysis with the ACCORDA software and hardware architecture

2019

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The data science revolution and growing popularity of data lakes make efficient processing of raw data increasingly important. To address this, we propose the ACCelerated Operators for Raw Data Analysis (ACCORDA) architecture. By extending the operator interface (subtype with encoding) and employing a uniform runtime worker model, ACCORDA integrates data transformation acceleration seamlessly, enabling a new class of encoding optimizations and robust high-performance raw data processing. Together, these key features preserve the software system architecture, empowering state-of-art heuristic optimizations to drive flexible data encoding for performance. ACCORDA derives performance from its software architecture, but depends critically on the acceleration of the Unstructured Data Processor (UDP) that is integrated into the memory-hierarchy, and accelerates data transformation tasks by 16x-21x (parsing, decompression) to as much as 160x (deserialization) compared to an x86 core. We evaluate ACCORDA using TPC-H queries on tabular data formats, exercising raw data properties such as parsing and data conversion. The ACCORDA system achieves 2.9x-13.2x speedups when compared to SparkSQL, reducing raw data processing overhead to a geomean of 1.2x (20%). In doing so, ACCORDA robustly matches or outperforms prior systems that depend on caching loaded data, while computing on raw, unloaded data. This performance benefit is robust across format complexity, query predicates, and selectivity (data statistics). ACCORDA's encoding-extended operator interface unlocks aggressive encoding-oriented optimizations that deliver 80% average performance increase over the 7 affected TPC-H queries.

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Section: Discussion and Related Workmentioning

confidence: 99%

Accelerating raw data analysis with the ACCORDA software and hardware architecture

2019

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“…R EGULAR EXPRESSIONS (REs) are widely used in several fields, from genome analysis [1] to text analytics [2] and Intrusion Detection Systems (IDSs) [3] for fast and efficient pattern matching tasks [4], [5]. The requirements of these applications and the high amounts of data to analyze make the performance of RE matching solutions crucial, keeping fostering research on this problem.…”

Section: Introductionmentioning

confidence: 99%

“…Many researchers address these challenges by efficiently representing the automata that accept the language defined by the RE [10], [11], [12]. In contrast, others exploit specialized hardware (e.g., ASICs or FPGAs [2], [13]) to build effective domain-specific solutions [14]. Indeed, reconfigurable devices demonstrate computing and energy efficiency advantages over generalpurpose processors [15], as well as higher adaptability than ASICs.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Domain-Specific Architecture for Regular Expressions

Conficconi

Sozzo

Carloni

et al. 2023

IEEE Trans. Emerg. Topics Comput.

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Regular Expressions (REs) are a computational kernel widely used for finding patterns in data in compute-intensive tasks such as genomic markers research, signature-based detection, and database query. Although flexible on the set of searched REs, software-based solutions cannot fulfill latency or throughput requirements to analyze massive data volumes at a given power budget. For this reason, many approaches exploit hardware accelerators as an offloading engine for REs matching. Indeed, various solutions rely on FPGA reconfigurability to embed automata into the reconfigurable fabric. However, this approach leads to time-consuming updates of the REs to search. This work exploits REs as sequences of basic instructions and builds a Domain-Specific Architecture (DSA), called TiReX, for RE matching on FPGAs. Our approach enables the user to change the desired RE at run-time, providing software programmability, flexibility, and specialized hardware mechanisms. Our DSA delivers performance in line with other state-of-the-art hardware approaches, while providing remarkable flexibility and we underline the importance of energy efficiency for these computations. We compared with multiple state-of-the-art software obtaining remarkable performance while achieving noticeable results with a better energy efficiency that ranges from 3× to 490× with our multi-core.

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“…It also lowers energy by combining memory access with logic operations. For instance, the seminal Automata Processor (AP) design [10], [35] outperform x86 CPUs by 256×, GPGPUs by 32×, and accelerator XeonPhi by 62× in the ANMLZoo benchmark suite [29], [34], while Cache Automaton (CA) [29] achieves 3.9× speedup over HARE [13] and 3× speedup over UAP [11].…”

Section: Introductionmentioning

confidence: 99%

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

Huang¹,

Chen²,

Li³

et al. 2021

Preprint

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Accelerating finite automata processing is critical for advancing real-time analytic in pattern matching, data mining, bioinformatics, intrusion detection, and machine learning. Recent in-memory automata accelerators leveraging SRAMs and DRAMs have shown exciting improvements over conventional digital designs. However, the bit-vector representation of state transitions used by all state-of-the-art (SOTA) designs is only optimal in processing worst-case completely random patterns, while a significant amount of memory and energy is wasted in running most real-world benchmarks.We present CAMA, a Content-Addressable Memory (CAM) enabled Automata accelerator for processing homogeneous nondeterministic finite automata (NFA). A radically different state representation scheme, along with co-designed novel circuits and data encoding schemes, greatly reduces energy, memory, and chip area for most realistic NFAs. CAMA is holistically optimized with the following major contributions: (1) a 16×256 8-transistor (8T) CAM array for state matching, replacing the 256×256 6T SRAM array or two 16×256 6T SRAM banks in state-of-theart (SOTA) designs; (2) a novel encoding scheme that enables content searching within 8T SRAMs and adapts to different applications; (3) a reconfigurable and scalable architecture that improves efficiency on all tested benchmarks, without losing support for any NFA that's compatible with SOTA designs; (4) an optimization framework that automates the choice of encoding schemes and maps a given NFA to the proposed hardware.Two versions of CAMA, one optimized for energy (CAMA-E) and the other for throughput (CAMA-T), are comprehensively evaluated in a 28nm CMOS process, and across 21 real-world and synthetic benchmarks. CAMA-E achieves 2.1×, 2.8×, and 2.04× lower energy than CA, 2-stride Impala, and eAP. CAMA-T shows 2.68×, 3.87× and 2.62× higher average compute density than 2-stride Impala, CA, and eAP. Both versions reduce the chip area required for the largest tested benchmark by 2.48× over CA, 1.91× over 2-stride Impala, and 1.78× over eAP.

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HARE: Hardware accelerator for regular expressions

Cited by 43 publications

References 24 publications

Accelerating raw data analysis with the ACCORDA software and hardware architecture

Accelerating raw data analysis with the ACCORDA software and hardware architecture

An Energy-Efficient Domain-Specific Architecture for Regular Expressions

CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories

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