Harmonic ring oscillator time-to-digital converter

Caram, Juan Pablo; Galloway, Jeff; Kenney, J.S.

doi:10.1109/iscas.2015.7168595

Cited by 7 publications

(5 citation statements)

References 6 publications

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“…The harmonic ring oscillator (HRO) is another effort for the same cause. It is a simple yet effective architecture 78 . HRO is also suitable to store the phase difference between multiple input edges.…”

Section: Ring Oscillator Tdcsmentioning

confidence: 99%

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Time‐to‐digital converters—A comprehensive review

Mattada

Guhilot

2021

Circuit Theory & Apps

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Summary This work presents a comprehensive literature review on different topologies of time‐to‐digital converters (TDCs). A brief history, applications, classification, characterization, and working principle of each TDC are mentioned. A survey of both Field Programmable Gate Array (FPGA) and Application‐Specific Integrated Circuit (ASIC) architectures is covered. The trade‐off with respect to applications, pros, and cons of different architectures and future scope of TDC as an alternative data converter is also explored.

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Section: Ring Oscillator Tdcsmentioning

confidence: 99%

“…It is a simple yet effective architecture. 78 HRO is also suitable to store the phase difference between multiple input edges.…”

Section: Harmonic Ring Oscillator Tdcmentioning

confidence: 99%

Time‐to‐digital converters—A comprehensive review

Mattada

Guhilot

2021

Circuit Theory & Apps

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“…Owing to the high reconfigurability of FPGAs, the FPGA-TDC also has the advantages of reconfigurable TDC architectures and integration with more functional logics. Numerous TDC architectures such as phased locks, delay lines, the Vernier method, and pulse shrinking have been implemented in FPGAs [15][16][17][18][19][20][21][22][23][24]. The harmonic ring oscillator structure achieved 347 ps bin size TDC in a Virtex-6 FPGA [15].…”

Section: Introductionmentioning

confidence: 99%

“…Numerous TDC architectures such as phased locks, delay lines, the Vernier method, and pulse shrinking have been implemented in FPGAs [15][16][17][18][19][20][21][22][23][24]. The harmonic ring oscillator structure achieved 347 ps bin size TDC in a Virtex-6 FPGA [15]. A 16-channel FPGA-TDC with 120 ps per LSB was implemented in a Virtex-4 FPGA for particle detectors [18].…”

Section: Introductionmentioning

confidence: 99%

Digital Integration of LiDAR System Implemented in a Low-Cost FPGA

et al. 2022

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With the development of artificial intelligence, LiDAR finds significant applications in robotics and autonomous driving. Aiming at increasing the compactness and the integration of 2-D LiDAR, this paper presents a highly digitally integrated 2-D LiDAR system implemented in a low-cost FPGA. The system is made of off-the-shelf components to limit the cost to USD 100. A laser transceiver with a symmetrical transmitting and receiving lens emits and collects laser pulses to range distance using the time-of-flight (ToF) method. As a key component in ToF, the FPGA-based time-to-digital converter (TDC) is adopted for counting the round-trip time of pulses, which is implemented in a low-cost FPGA of ZYNQ7010 with limited resources. The symmetrical structure of the delay line is used to design a more efficient TDC. The FPGA-TDC enables flexibility of design and integration with more functional logics and is microcontroller-free. All the digital logics including data processing and controlling are integrated into an FPGA with the TDC logics to realize fully digital integration and compact dimensions. The utilization of the whole architecture in the FPGA is about 15%. The experimental results demonstrated that the ranging accuracy of the LiDAR is about 2 cm, which is suitable for consumer electronics.

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“…This approach considers the oscillator as a TD memory element analogous to a capacitor in a Gm-C circuit. The resulting circuit is operated asynchronously but the concept of TD memory can also be found in clocked time to digital converters (TDC) [23]. Furthermore, the auxiliary digital subsystem will feature additional functionality and flexibility in terms of event-driven/nonlinear outputs and gain control.…”

Section: Introductionmentioning

confidence: 99%

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

Leene

Constandinou

2017

IEEE Trans. Circuits Syst. I

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The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems

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Harmonic ring oscillator time-to-digital converter

Cited by 7 publications

References 6 publications

Time‐to‐digital converters—A comprehensive review

Time‐to‐digital converters—A comprehensive review

Digital Integration of LiDAR System Implemented in a Low-Cost FPGA

Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

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