A simple yet high performance time-to-digital converter (TDC) architecture is proposed in this paper. Its key advantage is its ability to sample-and-hold a time interval and thereafter oversample the stored quantity to provide sub-gate delay resolution and high linearity. The converter is fully digital, synthesizable from standard logic cells, and owes its properties to the time storage mechanism which relies on injecting more than one signal edge into a ring oscillator and tracking their relative angle. Results from a prototype on FPGA reveal excellent noise suppression by achieving a single-shot precision of 0.05 times the unit inverting logic cell delay in the ring oscillator by using an oversampling ratio of 64.

No abstract

No abstract

An all-digital phase locked loop (ADPLL) that uses a second fractional-N PLL as its digitally-controlled oscillator (DCO) has been studied, prototyped and tested. This technique allows for an effective implementation of a low-bandwidth AD PLL, exploiting the benefits of a digital implementation while avoiding the complexity of designing a DCO and a Time-to-digital converter (TDC). The reuse of a PLL as a DCO provides for easy interfacing, high linearity, zero drift and very high frequency resolution. An overview of the theory, technique, limitations, applications, and results are presented in this paper.