Harp test structure to electrically determine size distributions of killer defects

Abstract

To improve accuracy of electrically based measurements of defect densities and defect size distributions, we present a novel Harp Test Structure (HTS). There, horizontal and vertical parallel lines will be placed inside a given boundary pad frame without using any additional active semiconductor devices. The enhanced two-dimensional (2D) permutation sequence provides that all neighborhood relationships of adjacent test structure lines are unique. This is the key to disentangle even multiple faults detected by fast digital measurements. For this reason, the number and size of individual defects will be extracted anywhere inside or in-between layers. Experimental results show, that not only optical measurements, but also electrical measurements at a Harp Test Structure are sufficient to get a precise defect size distribution that enables size distribution modeling for yield prediction.

Derivation and implication of a novel DRAM bit cost model

“…The parameter depends on the environment of the LSI fabrication line. The data reported from various fabricators shows a value of about 3 [3], [5]. In the case , (6) becomes simpler as (7) This indicates that the effective critical area does not change by chip shrink, which agrees with the results reported in a special case with parallel stripe patterns [6].…”

“…Then, is given as (4) where . On the other hand, if the chip is enlarged proportionally by increasing the number of transistors by a factor of will increase in proportion to for the same value and hence (5) In the case where both of the above instances occur simultaneously, the effective average number of defects on a chip is given as (6) where is the rate of the design rule shrink, is the rate of the transistor count increase and is the original effective critical area before the chip shrink and the transistor count increase. This provides a generalized formula for the effective critical area.…”

“…The wafer diameter parameter, , was set to be 2 because it has been the trend in past decades. According to (5), for 256M DRAM in 1999 can be estimated as four times that of 64M DRAM which utilizes the 256M DRAM cell structure. Although the actual yield data are not available from the industry, it is generally recognized that 64M DRAM chip yield was well over 80% in 1999.…”

Defect reduction in Cu dual damascene process using short-loop test structures

“…The data in the figure is separated according to defect size, corresponding to the total defect count detected by inline defect inspection after Cu CMP of several wafers. Most reports have indicated that is inversely proportional to the second or third power of [8]- [11]. However, the shape of the distribution in Fig.…”

Yield modeling of elliptical defect

“…More than one and a half of outlines of defects resemble ellipse, which is usually modeled as a circle in the yield model, which causes the errors estimation for IC [9,10]. This paper discusses the yield model and its correlative critical area model for an elliptical defect.…”