HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing

Abstract

Abstract-In this paper we present the HAsim FPGAaccelerated simulator. HAsim is able to model a sharedmemory multicore system including detailed core pipelines, cache hierarchy, and on-chip network, using a single FPGA. We describe the scaling techniques that make this possible, including novel uses of time-multiplexing in the core pipeline and on-chip network. We compare our timemultiplexed approach to a direct implementation, and present a case study that motivates why high-detail simulations should continue to play a role in the architectural exploration process.

Fast scalable FPGA-based Network-on-Chip simulation models

“…not neighboring) sets of routers are simulated at the same time. This issue has been studied in previous work [5] and a straightforward way to resolve it would be through a separate preprocessing step that identifies independent sets of routers in the network and then generates a fixed valid simulation schedule.…”

“…As has been shown in previous work [5], [6], time-multiplexing in the context of network simulation requires special care to retain proper ordering of events and careful state management to ensure that all routers in the network have a consistent view of the system. For instance, within a single target cycle, a router might send traffic to routers that were simulated in previous host cycles, but also send traffic to routers that will be simulated in subsequent host cycles.…”

High-Level Debugging and Verification for FPGA-Based Multicore Architectures

“…That is the case of RAMP Gold [17] and FAST [18]. In contrast, HaSim [19] and Arete [13] use A-Ports or Latency-Insensitive Bounded Data-flow Networks, which decouple FPGA cycles from model cycles while guaranteeing cycle-accuracy. HaSim uses time multiplexing, which does not scale.…”

An Area Optimized Robust Router Design Implementation

“…4 The packet receiver will then wait until it has enough space to hold the bytes of the packet and then respond with the assertion of the read_enb_X (read_enb_0, read_enb1 or read_enb_2) signal that is an input to the router. 5 The read_enb_X (read_enb0, read_enb_1 or read_enb_2) input signal can be asserted on the rising/falling clock edge in which data are read from the data_out_X (data_out_0, data_out_1 or data_out_2) bus. 6 As long as the read_enb_X (read_enb_0, read_enb_1 or read_enb_2) signal remains active, the data_out_X (data_out_0, data_out_1 or data_out_2) bus drives a valid packet byte on each rising clock edge.…”