HDL code generation from UML/MARTE sequence diagrams for verification and synthesis

Ebeid, Emad; Fummi, Franco; Quaglia, Davide

doi:10.1007/s10617-014-9158-1

Cited by 8 publications

(4 citation statements)

References 15 publications

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“…For this purpose, the transformation step of UML models to an executable model is necessary. Therefore, transformation tool has been developed to extract design information from UML models and represent it by an intermediate representation (2) to generate executable code such as SystemC/TLM or VHDL (3) [11]. The simulation results such as throughput and latency can be generated and back-annotated (4) to the original UML model for further refinement.…”

Section: Proposed Methodologymentioning

confidence: 99%

“…There is few literature proposing methodologies to generate executable models for functional verification from UML [11]- [14], SysML [15], and modeling and analysis of real time and embedded systems (MARTE) [16]- [18]. Mischkalla et al [19] and Mueller et al [20] introduce a set of UML profiles for co-modeling of HW/SW systems and a code generation scheme for co-simulation support.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Model-Driven Design of Network Aspects of Distributed Embedded Systems

Ebeid

Fummi

Quaglia

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model. Index Terms-Modeling and analysis of real time and embedded systems (MARTE), network manipulation, network synthesis, simulation, SystemC/transaction level modeling (TLM), unified modeling language (UML).

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Section: Proposed Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Model-Driven Design of Network Aspects of Distributed Embedded Systems

Ebeid

Fummi

Quaglia

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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“…e modeling of embedded systems with UML has been the subject of several research works [9,[24][25][26][27]. However, few of them deal with DPR features at high abstraction level.…”

Section: Related Workmentioning

confidence: 99%

A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM

Allem

Bourennane

Khelfaoui

2021

International Journal of Reconfigurable Computing

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To deal with the complex design issues of Dynamically Reconfigurable Systems-on-Chip (DRSoCs), it is extremely relevant to raise the abstraction level in which models are expressed. A high abstraction level allows great flexibility and reusability while bypassing low-level implementation details. In this context, model-driven engineering (MDE) provides support to build and transform precise and structured models for a particular purpose at different levels of abstraction. Indeed, high-level models are successively refined to low-level models until reaching the executable ones. Thus, this paper presents an MDE-based framework for DRSoCs design enabling the transformation of UML/MARTE specifications to SystemC/TLM implementation. To achieve a high degree of expressiveness for modeling dynamic reconfiguration, we use a suitable software engineering approach based on service-oriented component architecture. Since MARTE does not cover the common features of dynamic reconfiguration domain and service orientation concepts, new stereotypes are created by refinement to add missing capabilities to the profile. Likewise, SystemC does not provide native support for dynamic reconfiguration, thus leading us to adopt a design pattern based solution for DRSoCs implementation in compliance with standards. The proposed framework is validated through a reconfigurable active 3-way crossover case study in which we demonstrate the practicability of the approach by gradual model transformations with reduced implementation effort and significant design productivity gain.

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“…Execution trace analysis is another important application of ccsl constraints. In the scheme of marte/ccsl, execution trace analysis is an effective way to design and debug real-time embedded systems [5]. Execution traces are produced by instrumented code.…”

mentioning

confidence: 99%

An SMT-Based Approach to the Formal Analysis of MARTE/CCSL

Zhang

Mallet

Zhu

2016

Formal Methods and Software Engineering

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International audienceMARTE (abbreviated for Modeling and Analysis of Real-Time and Embedded systems) is a UML profile which provides a generalmodeling framework to design and analyze real-time embedded systems. CCSL (abbreviated for Clock Constraint Specification Language) is aformal language companion to MARTE, used to specify the constraints between the occurrences of events in real-time embedded systems. Many approaches have been proposed to the formal analysis of CCSL such as simulation and model checking. We propose in this paper an SMT-based approach to the formal analysis of CCSL. It is well-known that the SMT-based approach can effectively overcome the state-explosion problem for model checking, and can also be used for theorem proving. The latter feature allows us to prove the invalidity of CCSL constraints, which most of the existing approaches lack. We implement the proposed approach in a prototype tool clyzer on top of K framework and use Z3 as theunderlying SMT solver

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HDL code generation from UML/MARTE sequence diagrams for verification and synthesis

Cited by 8 publications

References 15 publications

Model-Driven Design of Network Aspects of Distributed Embedded Systems

Model-Driven Design of Network Aspects of Distributed Embedded Systems

A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM

An SMT-Based Approach to the Formal Analysis of MARTE/CCSL

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