HDL Library of Processing Units for an Automatic LDPC Decoder Design

Falcão, Gabriel; Gomes, Marco; Gonçalves, João; Faia, Pedro; Silva, V.

doi:10.1109/rme.2006.1689967

Cited by 6 publications

(4 citation statements)

References 9 publications

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“…Quaglio et al propose a solution [5] for the irregular network connecting BNs and CNs according to the Tanner graph. A complete coder/decoder low-power solution based on VLSI is presented in [7], while reconfigurable solutions based on FPGAs are proposed in [8][9]. However, these implementations have reduced flexibility and use high non-recurring engineering.…”

Section: Discussionmentioning

confidence: 99%

Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach

Falcão

Yamagiwa

Silva

et al. 2009

J. Comput. Sci. Technol.

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Low-Density Parity-Check (LDPC) codes are powerful error correcting codes adopted by recent communication standards. LDPC decoders are based on belief propagation algorithms, which make use of a Tanner graph and very intensive message-passing computation, and usually require hardware-based dedicated solutions. With the exponential increase of the computational power of commodity graphics processing units (GPUs), new opportunities have arisen to develop general purpose processing on GPUs. This paper proposes the use of GPUs for implementing flexible and programmable LDPC decoders. A new stream-based approach is proposed, based on compact data structures to represent the Tanner graph. It is shown that such a challenging application for stream-based computing, because of irregular memory access patterns, memory bandwidth and recursive flow control constraints, can be efficiently implemented on GPUs. The proposal was experimentally evaluated by programming LDPC decoders on GPUs using the Caravela platform, a generic interface tool for managing the kernels' execution regardless of the GPU manufacturer and operating system. Moreover, to relatively assess the obtained results, we have also implemented LDPC decoders on general purpose processors with Streaming Single Instruction Multiple Data (SIMD) Extensions. Experimental results show that the solution proposed here efficiently decodes several codewords simultaneously, reducing the processing time by one order of magnitude.

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Section: Discussionmentioning

confidence: 99%

Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach

Falcão

Yamagiwa

Silva

et al. 2009

J. Comput. Sci. Technol.

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show abstract

“…Attending to the zigzag connectivity [8] between PNs and CNs defined by B in (9), they are updated jointly in CN mode [5]. An efficient VLSI architecture has been proposed in [28,29], where the joint processing of CNs and PNs is performed as depicted in Figure 3. For example, when updating PN m , according to (6) it becomes a passing node because the message it sends to CN m+1 is the message received from CNm added to the channel information, and vice-versa (see Figure 3).…”

Section: Parallel M-kernel Ldpc Decoder Architectures For Dvb-s2mentioning

confidence: 99%

“…Under this context we developed a novel hardware approach, originally proposed in [14,28], which is based on a partial-parallel architecture that simplifies the barrel shifter and reduces memory requirements. We address the generalization of the well known M-kernel parallel hardware structure [5] and propose its partitioning by any integer L submultiple of M (which can be obtained from the decomposition of M = 360 = 2 3 × 3 2 × 5), without memory addressing/reconfiguration overheads and keeping unchanged the efficient message-passing mechanism.…”

Section: M-factorizable Vlsi Parallel Ldpc Decoder Architecture For Dmentioning

confidence: 99%

“…This approach does not only surpass some disadvantages of the architecture described in [5], such as die area occupied or routing congestion, but it also adds flexibility and reconfigurability to the system according to the decoder requirements and device constraints. This type of sub-sampling approach preserves the key modulo-m properties of the architecture [5], with only P = M/L processing units addressed in [28,29] as shown in Figure 2. This strategy allows a linear reduction by L of the hardware resources occupied by the FU blocks, and reduces significantly the complexity (2 × O(P log P)) of the interconnection network (or barrel shifter), which simplifies the routing problem.…”

Section: M-factorizable Vlsi Parallel Ldpc Decoder Architecture For Dmentioning

confidence: 99%

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Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design

Falcão

Gomes

Silva

et al. 2012

J Wireless Com Network

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Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm 2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption.

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