HDL Program Slicing to Reduce Bounded Model Checking Search Overhead

Abstract

The size of the Hardware Description Model for a complex modern digital system is increasing rapidly. CAD tools used to analyze these models are challenged by this increase in model complexity. In this paper, we present a technique that extracts for a given set of variables, a smaller HDL executable design slice that includes all the behavioral elements that affect those variables directly or indirectly. The design slice when compiled produces a behavior for the set of variables equivalent to the one computed by the original unsliced design. ATPG and verification tools analyzing this design could use the sliced model to reduce computation overhead. We implemented this technique in a computer program and evaluated its impact on the bounded model checker, SMV. Our results show a reduction for both CPU time and memory needed by SMV to verify a publicly available model of the USB 2.0 IP core.

A Visual Dependency Analysis Method Based on VHDL

“…The increasing complexity of integrated circuit in compute systems poses a challenge to hardware formal verification [1]. Many model verification approaches are proposed for hardware description languages (HDL).…”