He-P2012: Architectural heterogeneity exploration on a scalable many-core platform

Abstract

Architectural heterogeneity is a promising solution to overcome the utilization wall and provide Moore's Law-like performance scaling in future SoCs. However, heterogeneous architectures increase the size and complexity of the design space along several axes: granularity of the heterogeneous processors, coupling with the software cores, communication interfaces, etc. As a consequence, significant enhancements are required to tools and methodologies to explore the huge design space effectively. In this work, we provide three main contributions: first, we describe an extension to the STMicroelectronics P2012 platform to support tightly-coupled shared memory HW processing elements (HWPE), along with our changes to the P2012 simulation flow to integrate this extension. Second, we propose a novel methodology for the semi-automatic definition and instantiation of HWPEs from a C program based on a interface description language. Third, we explore several architectural variants on a set of benchmarks originally developed for the homogeneous version of P2012, achieving up to 123x speedup for the accelerated code region (∼98% of the Amdahl limit for the whole application), thereby demonstrating the efficiency of tightly memory-coupled hardware acceleration.

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

“…Moreover, contrarily to previous work in this category of accelerators, we propose a full-fledged flow that allows fast design exploration of heterogeneous clusters, with semi-automatic generation of HWPEs and estimation of power and area consumption based on RTL synthesis results. With respect to our previous work in [12], we improved our design flow by adding #pragmas that directly control not only the high-level synthesis tool, but also the subsequent logical synthesis tool. Moreover, we developed two new benchmarks for P2012 (one based on Convolutional Neural Networks, the other on Mahalanobis Distance) and accelerated them using our design flow.…”

“…In this work, we extend and complete our previous work in [12] where we augmented the STMicroelectronics P2012 cluster with tightlycoupled shared-L1 memory hardware processing elements (HWPEs). HWPEs can be used to increase performance and/or energy efficiency of the P2012 homogeneous clusters.…”

Energy-efficient vision on the PULP platform for ultra-low power parallel computing

“…Also some commercial products follow this path: for example the Analog Devices Blackfin [16], which features a fixed-function Pipelined Vision Processor for CV acceleration. Another approach is to augment an existing many-core with accelerator cores, as is done in He-P2012 [17].…”

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

“…In this work, we propose the 65 nm Fulmine secure data analytics System-on-Chip (SoC), which tackles the two main limiting factors of IoT end-nodes while providing full programmability, low-effort data exchange between processing engines, (sufficiently) high speed, and low energy. The SoC is based on the architectural paradigm of tightly-coupled heterogeneous shared-memory clusters [11], where several engines (which can be either programmable cores or specialized hardware accelerators) share the same first-level scratchpad via a low-latency interconnect. In Fulmine, the engines are four enhanced 32-bit OpenRISC cores, one highly efficient cryptographic engine for AES-128 and KECCAK-based encryption, and one multi-precision convolution engine specialized for CNN computations.…”