Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system

Abstract

Phase change memory (PCM) is emerging as a promising solution for future memory systems and disk caches. As a type of resistive memory, PCM relies on the electrical resistance of Ge 2 Sb 2 Te 5 (GST) to represent stored information. With the adoption of multi-level programming PCM devices, unwanted resistance drift is becoming an increasing reliability concern in future high-density, multi-level cell PCM systems. To address this issue without incurring a significant storage and performance overhead in ECC, conventional design employs a conservative approach, which increases the resistance margin between two adjacent states to combat resistance drift. In this paper, we show that the wider margin adversely impacts the lowpower benefit of PCM by incurring up to 2.3X power overhead and causes up to 100X lifetime reduction, thereby exacerbating the wear-out issue. To tolerate resistance drift, we proposed Helmet, a multi-level cell phase change memory architecture that can cost-effectively reduce the readout error rate due to drift. Therefore, we can relax the requirement on margin size, while preserving the readout reliability of the conservative approach, and consequently minimize the power and endurance overhead due to drift. Simulation results show that our techniques are able to decrease the error rate by an average of 87%. Alternatively, for satisfying the same reliability target, our schemes can achieve 28% power savings and a 15X endurance enhancement due to the reduced margin size when compared to the conservative approach.

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

“…If cell resistance reaches that of the next level, the value read from the cell may be different from that originally stored, and thus, drift can lead to errors (refer to Figure 2). A rise in temperature, e.g., due to 3D-stacking, further increases the drift errors [17,18]. [13,[18][19][20] and tri-level cell [2,21].…”

“…2. In MLC PCM, the resistance margins between consecutive levels increase exponentially, for example when the ratio of consecutive resistance values is five (i.e., R 00 /R 01 = R 01 /R 10 = R 10 /R 11 = 5), data remain valid for two years; however, if this ratio is two, the data remain valid for 1 h only (assuming room temperature) [17]. Thus, a simple strategy to address drift errors is to widen the resistance margin between neighboring states.…”

“…Thus, a simple strategy to address drift errors is to widen the resistance margin between neighboring states. This, however, requires increasing the resistance of the largest resistance states [17], which degrades endurance and energy efficiency due to the requirement of increased programming current. The write endurance of MLC PCM is much smaller than that of SLC PCM (10 5 vs. 10 8 writes), and drift mitigation mechanisms may further aggravate the endurance issue [3,16,17], for example due to scrub operations or increased resistance margins.…”

“…11. Due to the limited write endurance of PCM, many PCM management techniques account for its endurance, as well [13,17,18,21,47,[50][51][52]. 12.…”

“…Some works statically divide the resistance spectrum such that larger margins are used for states with a higher drift rate [21,50]. Some works perform memory page allocation in a temperature-aware manner [17], whereas others perform the runtime transition of a memory page or a cache block between drift-prone MLC and drift-free SLC [17,49]. We now review some of these works.…”