HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs

Wächter, Eduardo; Biazi, Adelcio; Moraes, Fernando

doi:10.1109/recosoc.2011.5981498

Cited by 8 publications

(2 citation statements)

References 11 publications

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“…Post-layout results show very low power, area, and high frequency [22]. Wächter et al presented an open source platform for MPSoC development named HeMPS Station which derived from the MPSoC HeMPS [23]. In its present state, it includes the platform (NoC, processors, DMA and NI), embedded software (microkernel and applications) and a dedicated Computer-Aided Design (CAD) tool to generate the required binaries and perform debugging.…”

Section: Related Workmentioning

confidence: 99%

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Salem¹,

Salah²,

Bennour³

et al. 2017

ijacsa

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Abstract-Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

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Section: Related Workmentioning

confidence: 99%

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Salem¹,

Salah²,

Bennour³

et al. 2017

ijacsa

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“…The platform provides modularity at processor level and can be exploited for the implementation of the iterative decoding of LDPC. HeMPS is an open source framework targeting MPSoC customisation that includes the platform comprising of NoC, processors and DMA, the embedded software comprising of microkernel and applications and a dedicated CAD tool to generate required binaries for implementation on FPGA platforms and perform debugging [9]. Communication between processors is done using the NoC communication structure and is implemented using message passing routines.…”

Section: Introductionmentioning

confidence: 99%

Parallel decoder for low density parity check codes: A MPSoC study

Kanur

Georgakarakos²,

Simla³

et al. 2013

2013 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its wide applications. Iterative decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. Recent trends in integrating Multiprocessor System on Chip (MPSoC) with Network on Chip (NoC) gives a modular platform for parallel implementation. This paper presents an implementation platform for decoding LDPC codes based on HeMPS, an open source MPSoC framework based on NoC communication fabric. Reduced minimum sum algorithm is used for decoding LDPC codes and simulations are performed using HeMPS tool. The data rate and speedup factor measured for decoding a rate 1/2 LDPC code characterised by 252 × 504 parity matrix is presented.

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