3rd Electronics System Integration Technology Conference ESTC 2010
DOI: 10.1109/estc.2010.5642954
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Hermetic wafer-level packaging development for RF MEMS switch

Abstract: This paper presents a low temperature «350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements:• Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance • Electrical connection between both wafers • Hermetic sealing under controlled atmosphere with 5 +1-0.5 /lm gap between … Show more

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Cited by 13 publications
(9 citation statements)
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“…[2][3][4][5][6][7][8][9][10][11][12][13][14] In so doing, leads must be drawn while maintaining vacuum, which is a problem especially in RF MEMS using low-resistance thick Au lines. 1 With high-frequency (RF) MEMS switches, internal space is usually retained in vacuum to prevent degradation of electric contacts, or to maintain switching speed through suppression of aid damping.…”
Section: Forewordmentioning
confidence: 99%
“…[2][3][4][5][6][7][8][9][10][11][12][13][14] In so doing, leads must be drawn while maintaining vacuum, which is a problem especially in RF MEMS using low-resistance thick Au lines. 1 With high-frequency (RF) MEMS switches, internal space is usually retained in vacuum to prevent degradation of electric contacts, or to maintain switching speed through suppression of aid damping.…”
Section: Forewordmentioning
confidence: 99%
“…For simplicity, TSVs locate in the cap wafer [303]- [305], but it is also possible to be in the substrate [306]. For both cases, the TSVs are used for RF signal transmission through the hermetically-sealed substrate or cap.…”
Section: Rf Memsmentioning
confidence: 99%
“…This paper presents a 0-level package based on chip capping. Two features in particular make the package very attractive and distinct from previous implementations [7][8][9][10]:…”
Section: Introductionmentioning
confidence: 98%
“…The length of the feedthroughs varies with the width of the sealing ring and the design is such that the microstrip line keeps a characteristic impedance identical to the CPW (typically 50 ) [6]. (3) Vertical via's, implemented either in the MEMS substrate [7,8,9] or in the Cap [10] as shown in Fig. 1, present a more compact solution (smaller footprint) than the horizontal feedthrough designs, but, the process is more complex as through-wafer hole etching is required.…”
Section: Introductionmentioning
confidence: 99%