Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

Vrudhula, Sarma; Wang, J.M.; Ghanta, Praveen

doi:10.1109/tcad.2005.862734

Cited by 86 publications

(76 citation statements)

References 11 publications

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“…In place of the sigmoid function, here we propose to use a set of orthonormal Hermite polynomial basis functions, taking advantage of their excellent approximation performance, as the activation functions in the hidden layer with the aim of attaining better performance in terms of accuracy and convergence [23,24]. The orthogonal Hermite polynomials are defined as follows:…”

Section: Ohpbnn Pa Behavioral Modelmentioning

confidence: 99%

Behavioral Modeling of Rf Power Amplifiers With Memory Effects Using Orthonormal Hermite Polynomial Basis Neural Network

Yuan¹,

Feng²

2013

PIER C

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Abstract-Behavioral modeling technique provides an efficient and convenient way to analyze and predict the performance of the RF power amplifiers (PAs) in system-level, and thus helps to construct a suitable predistorter to linearize the PA system. To accurately describe the nonlinear dynamic characteristics of PAs, an orthonormal Hermite polynomial basis neural network (OHPBNN) is utilized to represent the PA behavioral model, which outperforms, mainly in respect of modeling accuracy, the classic feedforward neural network using sigmoid activation functions.In addition, we apply an adaptive algorithm to determine the appropriate memory depth of PA behavioral model. Simulation results show that the proposed model provides more accurate prediction of the PAs output signal compared with classic neural network models.

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Section: Ohpbnn Pa Behavioral Modelmentioning

confidence: 99%

Behavioral Modeling of Rf Power Amplifiers With Memory Effects Using Orthonormal Hermite Polynomial Basis Neural Network

Yuan¹,

Feng²

2013

PIER C

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“…To address the effect, great amount of research has been done recently, such as the clock skew analysis under process variation [4][5][6][7][8][9][10], statistical performance analysis [9,10], worst case performance analysis [11,12], parametric yield estimation [12,13], impact analysis on micro architecture [12,13] and delay fault [14,15] test under process variation [14][15][16][17]. As the technology reaches deep submicron or nanometer regime, the errors due to process variations becomes prominent [17][18][19]. Threshold voltage of a MOSFET varies due to (1) Changes in oxide thickness; (2) Substrate, polysilicon and implant impurity level; (3) Surface charge.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

Verma¹,

Kaushik²,

Singh³

2011

IJCA

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Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. Threshold voltage of a MOSFET varies due to changes in oxide thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of threshold variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced threshold variations on circuit delay is discussed for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

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“…Process variation has been the topic of many lines of research; see, for instance, [6,7,11,58,69,117]. Similarly, workload uncertainty has not been deprived of attention; see, for instance, [32,88,96,98,105,124].…”

Section: Previous Workmentioning

confidence: 99%

“…Static power is also quantified in [7] via the pc and kl techniques. The same combination of tools is employed in [117] and [44] in order to analyze the response of interconnect networks and power grids, respectively, under process variation.…”

Section: Previous Workmentioning

confidence: 99%

“…The last five of the above techniques, that is, [6,7,44,99,117], perform only probabilistic power analysis and ignore the interdependence between power and temperature described in Section 2.2. The other ones are temperaturerelated approaches, but none of them attempts to tackle probabilistic transient analysis, that is, to compute the probability distributions of power and temperature that evolve over time.…”

Section: Previous Workmentioning

confidence: 99%

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System-Level Analysis and Design under Uncertainty

Ukhov¹

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One major problem for the designer of electronic systems is the presence of uncertainty, which is due to phenomena such as process and workload variation. Very often, uncertainty is inherent and inevitable. If ignored, it can lead to degradation of the quality of service in the best case and to severe faults or burnt silicon in the worst case. Thus, it is crucial to analyze uncertainty and to mitigate its damaging consequences by designing electronic systems in such a way that uncertainty is effectively and efficiently taken into account.We begin by considering techniques for deterministic system-level analysis and design of certain aspects of electronic systems. These techniques do not take uncertainty into account, but they serve as a solid foundation for those that do. Our attention revolves primarily around power and temperature, as they are of central importance for attaining robustness and energy efficiency. We develop a novel approach to dynamic steady-state temperature analysis of electronic systems and apply it in the context of reliability optimization.We then proceed to develop techniques that address uncertainty. The first technique is designed to quantify the variability in process parameters, which is induced by process variation, across silicon wafers based on indirect and potentially incomplete and noisy measurements. The second technique is designed to study diverse system-level characteristics with respect to the variability originating from process variation. In particular, it allows for analyzing transient temperature profiles as well as dynamic steady-state temperature profiles of electronic systems. This is illustrated by considering a problem of design-space exploration with probabilistic constraints related to reliability. The third technique that we develop is designed to efficiently tackle the case of sources of uncertainty that are less regular than process variation, such as workload variation. This technique is exemplified by analyzing the effect that workload units with uncertain processing times have on the timing-, power-, and temperature-related characteristics of the system under consideration.We also address the issue of runtime management of electronic systems that are subject to uncertainty. In this context, we perform an early investigation into the utility of advanced prediction techniques for the purpose of finegrained long-range forecasting of resource usage in large computer systems.All the proposed techniques are assessed by extensive experimental evaluations, which demonstrate the superior performance of our approaches to analysis and design of electronic systems compared to existing techniques. The research presented in this thesis has been partially funded by the National Computer Science Graduate School (cugs) in Sweden.v Sammanfattning Ett stort problem för designern inom elektroniska system är förekomsten av osäkerhet, som beror på sådana fenomen som variationer relaterade till tillverkning och arbetsbelastning. Osäkerhet är i många fall naturlig och oundv...

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Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

Cited by 86 publications

References 11 publications

Behavioral Modeling of Rf Power Amplifiers With Memory Effects Using Orthonormal Hermite Polynomial Basis Neural Network

Behavioral Modeling of Rf Power Amplifiers With Memory Effects Using Orthonormal Hermite Polynomial Basis Neural Network

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

System-Level Analysis and Design under Uncertainty

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