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Deformations in interconnect due to process variations can lead to significant performance degradation in deep submicron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplfied models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual emr: The key advance of the proposed method is that itpmvides afunctional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA. Results f " OPERA simulations on commercial design test cases match well with thosef" the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational eficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations. IntroductionThe performance of integrated circuits (ICs) is increasingly less predictable as device dimensions shrink below the sub-100 nanometer scale. The modeling accuracy problem stems from poor control of the physical device and interconnect characteristics during the manufacturing process. Uncertainties due to variations in the manufacturing process are reflected in variations in the circuit parameters. Examples of manufacturing variations are the variations in materials,

In this paper, we investigate the impact of interconnect and device

In this paper 1 we propose a framework for Statistical Static Timing Analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations.

This paper proposes the use of Karhunen-Loève Expansion (KLE) for accurate and efficient modeling of intra-die correlations in the semiconductor manufacturing process. We demonstrate that the KLE provides a significantly more accurate representation of the underlying stochastic process compared to the traditional approach of dividing the layout into grids and applying Principal Component Analysis (PCA). By comparing the results of leakage analysis using both KLE and the existing approaches, we show that using KLE can provide up to 4 − 5× reduction in the variability space (number of random variables) while maintaining the same accuracy. We also propose an efficient leakage minimization algorithm that maximizes the leakage yield while satisfying probabilistic constraints on the delay.