HETERO-SCHED: A Low-Overhead Heterogeneous Multi-core Scheduler for Real-Time Periodic Tasks

Moulik, Sanjay; Devaraj, Rajesh; Sarkar, Arnab

doi:10.1109/hpcc/smartcity/dss.2018.00117

Cited by 17 publications

(10 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Task scheduling process belongs to one of the most important procedures during the designing of the real-time applications as it decides about appropriate and optimal resource utilisation and overall quality of the system [2,[26][27][28][29][30][31][32]. That is why this phase of the contemporary real-time system manufacturing belongs to one of the most crucial issues.…”

Section: Tasks Scheduling Mechanismmentioning

confidence: 99%

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

show abstract

Section: Tasks Scheduling Mechanismmentioning

confidence: 99%

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Antolak

Pułka

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…In this specific context, the template schedule is built using Mc Naughton wrap-around rule [9]. More recently, a heuristic to schedule periodic tasks on unrelated multiprocessor platforms has been proposed in [10], with in general, an exponential complexity.…”

Section: A Related Workmentioning

confidence: 99%

“…As the seminal work is focused on the feasibility, repeating the template schedule every unit of time is theoretically acceptable. Papers [8], [10] also rely on the notion of the template schedule, although it is differently built. Nevertheless, the authors propose a more applicable solution in stretching the template schedule into consecutive intervals of time delimited by absolute deadlines (referred to as deadline partitioning [5]), in a third step.…”

Section: Rate Matrixmentioning

confidence: 99%

Template schedule construction for global real-time scheduling on unrelated multiprocessor platforms

Bertout

Goossens

Grolleau

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

The seminal work on the global real-time scheduling of periodic tasks on unrelated multiprocessor platforms is based on a two-step method. First, the workload of each task is distributed over the processors and it is proved that this first step success ensures the existence of a feasible schedule. Then, using this workload assignment as an input, a template schedule construction method is presented. In this work, we review the seminal work and show by using a counterexample that this second step is incomplete. Thus, we propose and prove correct a novel and efficient algorithm to build the template schedule.

show abstract

“…Moulik et al . [20] proposed a deadline partitioning (DP)‐Fair [6] based heuristic approach for the scheduling of real‐time tasks executing on heterogeneous platforms. It may be noted that the works in [18–20] discussed above, mainly focus on satisfying timing related constraints associated with real‐time systems and they do not consider energy minimisation as part of their scheduling objective.…”

Section: Related Workmentioning

confidence: 99%

HEALERS: a heterogeneous energy‐aware low‐overhead real‐time scheduler

Moulik

Devaraj

Sarkar

2019

IET Computers & Digital Techniques

Self Cite

View full text Add to dashboard Cite

HETERO-SCHED: A Low-Overhead Heterogeneous Multi-core Scheduler for Real-Time Periodic Tasks

Cited by 17 publications

References 13 publications

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Flexible hardware approach to multi‐core time‐predictable systems design based on the interleaved pipeline processing

Template schedule construction for global real-time scheduling on unrelated multiprocessor platforms

HEALERS: a heterogeneous energy‐aware low‐overhead real‐time scheduler

Contact Info

Product

Resources

About