Heteroepitaxial Growth of III-V Semiconductors on Silicon

Abstract

Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.

ULTRARAM: A Low‐Energy, High‐Endurance, Compound‐Semiconductor Memory on Silicon

“…[ 5–8 ] Therefore, the integration of the complementary technologies of III–Vs and Si is highly desirable for many applications. [ 9 ] This has historically been carried out by wafer bonding techniques, but such approaches have drawbacks such as added complexity of fabrication and differences of wafer size, often resulting in inefficient use of substrate material. [ 10 ] More recently, heterogeneous epitaxy has offered a promising route toward the efficient cointegration of III–Vs and Si.…”

Selective-Area Epitaxy of InGaAsP Buffer Multilayer for In-Plane InAs Nanowire Integration

“…Moreover, one-dimensional (1D) InAs channels can be proximitized by superconductors to realize topological superconductor networks and quantum devices [ 1 , 2 , 3 , 4 , 5 ]. However, the monolithic integration of InAs in the silicon technology requires the development of a buffer layer accommodating the large lattice mismatch (11.6% between InAs and Si) and to solve the problem of anti-phase domain (APD) formation [ 6 ]. The latter can be overcome with the epitaxial growth of a GaP interfacial layer on Si (100) substrates.…”

High Speed Evanescent Quantum‐Dot Lasers on Si

“…Quantum dot (QD) gain material is attractive for this application due to its unique atom‐like density of states, and in particular the improved tolerance to defects, reduced reflection sensitivity, nearly zero linewidth enhancement factor, low transparency current density, and excellent optical gain thermal stability. [ 5–8 ] Performance of heteroepitaxially grown QD devices on industry‐standard Si substrates has been proven to match that of heterogeneously bonded quantum well (QW) devices, and has quickly closed the gap in terms of static performance, reliability, etc., compared to devices grown on native substrates. [ 9 ] However, relatively thick buffer layers are needed in such epitaxial approaches which makes coupling to adjacent photonic circuits challenging, and there is no clear roadmap yet for scalable monolithic integration of III–Vs on Si on insulator (SOI)‐based waveguides using a planar growth geometry.…”