2013
DOI: 10.1142/s0218126613500163
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Heterogeneous 3d Network-on-Chip Architectures: Area and Power Aware Design Techniques

Abstract: Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip°oorplan compared to a 2D router. Hence, more e±cient architectures should be designed. In this paper, we propose area e±cient and low power 3D heterogeneous NoC archi… Show more

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Cited by 21 publications
(14 citation statements)
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“…We compare with conventional channel model where signals are transmitted over pure air with no MAA (e.g. two-ray channel model in [20]) 2 .…”
Section: Simulation Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…We compare with conventional channel model where signals are transmitted over pure air with no MAA (e.g. two-ray channel model in [20]) 2 .…”
Section: Simulation Resultsmentioning
confidence: 99%
“…5 that the total path loss in the conventional channel model is independent of the ambient pressure. However, the total path loss in the proposed channel 2 In our model, the parameterizable medium compositions consist of water vapour (which could also an effect of emerging liquid cooling technology), carbon dioxide, oxygen, nitrogen, ozone, molecular hydrogen, nitrous oxide, methane, dioxygen, nitrogen oxide, sulfur dioxide, acetylene, ethane, ethylene, methanol, hydrogen cyanide, chloromethane, hydroxyl radical, hydrogen chloride, chlorine monoxide, carbonyl sulfide, formaldehyde, hypochlorous acid, hydrogen peroxide, phosphine, carbonyl fluoride, sulfur hexafluoride, hydrogen sulfide, formic acid, hydroperoxyl radical, chlorine nitrate, nitrosonium ion, hypobromous acid, bromomethane, acetonitrile, carbon tetrafluoride, diacetylene, cyanoacetylene, carbon monosulfide, sulfur trioxide. 3 Note that 1atm = 101.325kPa 6, the total path loss of various channel models is plotted.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…Based on the serialization methodology, Pasricha [36] proposed a 3D NoC synthesis framework; their approach adopt routers that have several local ports, which have high power consumption due to the increased number of ports and high data rates across the crossbar. On the other hand, existing inhomogeneous architectures (Figure 3a) [1,2,32,33,[37][38][39][40][41][42] do not consider the dynamics of application traffic load in their inhomogeneous architectures. Applications in such 3D NoCs are not optimized, as communication bandwidth and performance constraints of the applications were not considered in the architecture generation.…”
Section: D Network-on-chipmentioning
confidence: 99%
“…1) [2], [22]- [25] however, do not consider the dynamics of application traffic load in their architectures generation. Applications in such 3D NoCs are not optimized as communication bandwidth and performance constraints of the applications were not considered in the architecture generation.…”
Section: A 3d Network-on-chip Architecturesmentioning
confidence: 99%
“…Moreover, Through Silicon Via (TSV) which has been accepted as a viable inter-layer wiring technique has a complex and expensive manufacturing process [1]. To optimize the performance and manufacturing cost of 3D NoCs with minimal distortion to the modularity, inhomogeneous architectures have been proposed to combine 2D and 3D routers in 3D NoCs [2]- [4]. Several inhomogeneous 3D architectures focusing on different NoC router architectures, minimal hopcount between 2D and 3D routers in each layer, and uniform distribution of 2D and 3D routers have been proposed [5].…”
Section: Introductionmentioning
confidence: 99%