Heterogeneous Clustered VLIW Microarchitectures

Aletà, Alex; Codina, Josep; González, Antonio; Kaeli, David

doi:10.1109/cgo.2007.15

Cited by 15 publications

(15 citation statements)

References 22 publications

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“…has a great impact on the quality of scheduling (2.). We observed that the estimation of the scheduling outcome without performing the actual scheduling, as done in [2], can be inaccurate. Nevertheless, it is a critical compilation decision since selecting a non-optimal frequency set can lead to a schedule with poor performance, energy consumption or both.…”

Section: Introductionmentioning

confidence: 92%

“…The second step performs scheduling on the architecture configuration selected by step 1. This includes both cluster assignment and instruction scheduling, which in an unmodified [2] are in two separate steps.…”

Section: Phase Orderingmentioning

confidence: 99%

“…The Decoupled algorithm (existing state-of-the-art based on [2]) is in Fig.2a. As already mentioned, there are two distinct steps:…”

Section: Phase Orderingmentioning

confidence: 99%

“…State-of-the-art work in this field ( [2]) treats these two sub-problems independently and solves the first (1.) before the second (2.).…”

Section: Introductionmentioning

confidence: 99%

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UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

Porpodas

Cintra

2013

Languages and Compilers for Parallel Computing

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Abstract. Clustered VLIW processors are scalable wide-issue statically scheduled processors. Their design is based on physically partitioning the otherwise shared hardware resources, a design which leads to both high performance and low energy consumption. In traditional clustered VLIW processors, all clusters operate at the same frequency. Heterogeneous clustered VLIW processors however, support dynamic voltage and frequency scaling (DVFS) independently per cluster. Effectively controlling DVFS, to selectively decrease the frequency of clusters with a lot of slack in their schedule, can lead to significant energy savings. In this paper we propose UCIFF, a new scheduling algorithm for heterogeneous clustered VLIW processors with software DVFS control, that performs cluster assignment, instruction scheduling and fast frequency selection simultaneously, all in a single compiler pass. The proposed algorithm solves the phase ordering problem between frequency selection and scheduling, present in existing algorithms. We compared the quality of the generated code, using both performance and energy-related metrics, against that of the current state-of-the-art and an optimal scheduler. The results show that UCIFF produces better code than the state-ofthe-art, very close to the optimal across the mediabench2 benchmarks, while keeping the algorithmic complexity low.

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Section: Introductionmentioning

confidence: 92%

Section: Phase Orderingmentioning

confidence: 99%

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UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

Porpodas

Cintra

2013

Languages and Compilers for Parallel Computing

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“…Clustered architectures [2,3,4,5] have been proposed to improve the scalability and performance by partitioning resources in critical timing paths like register files among clusters. However, the scalability achieved this way is still limited by traditional instruction encoding and centralized instruction execution control.…”

Section: Introductionmentioning

confidence: 99%

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control

Chen

Wang

et al. 2011

IEICE Electron. Express

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Abstract:The scalability achieved by partitioning of resources among clusters is still limited by traditional instruction encoding and centralized instruction execution control. This paper introduces a scalable unicore clustered architecture (SUCA). The instruction encoding encodes common information of sequences of instructions separately, thus reducing the amount of information in instruction words. The pipeline allows functional units to manage their own execution, thus releasing instruction issuing from instruction scheduling. SUCA can scale to 32 clusters with 1024 registers. Meanwhile, for the 4-cluster configuration, SUCA achieves an average of 13.3% speedup and a 4.6% improvement in frequency with reasonable hardware overhead, as compared with a traditional clustered processor.

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