Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials

IEEE J. Electron Devices Soc.

Roh

Han

et al. 2021

Self Cite

In this study, we demonstrated low leakage current and high mobility thin body (In)GaSb p-FETs. Through the optimization of the V/III ratio during the epitaxial growth, we achieved a highly insulating bottom Al0.95Ga0.05Sb barrier, which eliminates the junction leakage. We also suppressed the interface trap-assisted surface leakage current by introducing In0.53Ga0.47As surface passivation on the GaSb channel. Furthermore, GaSb/InGaSb/GaSb quantum well (QW) channel structure provided significant improvement in effective mobility (μeff) characteristics. As a result, the fabricated devices showed the lowest off-leakage current (Ioff), subthreshold slope (S.S.) and high μeff among reported GaSb p-MOSFETs.

Section: Evaluation Of Interface and Channel Qualitymentioning

confidence: 99%

High Hole Mobility and Low Leakage Thin-Body (In)GaSb p-MOSFETs Grown on High-Bandgap AlGaSb

IEEE J. Electron Devices Soc.

Roh

Han

et al. 2021

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“…In contrast, III–V channel materials are a promising candidate for M3D integration due to low process temperature and high potential logic performance as well as multifunctionality such as imaging, display, photonic sensors, and so forth. − In this work, therefore, we suggest 3D stackable III–V synaptic transistors fabricated at low process temperatures. Here, we used an oxide charge trap layer for weight storage because the oxide layer can be deposited at quite low temperatures uniformly by atomic layer deposition (lower than 350 °C) and it shows very stable operation, as seen in the NAND flash technology.…”

Section: Introductionmentioning

confidence: 99%

3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks

ACS Appl. Mater. Interfaces

Jeong

Bidenko

et al. 2020

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Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III–V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (αp/αd = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics.

“…Monolithic three-dimensional (M3D) integration with III-V compound semiconductor (e.g., InGaAs) offers many advantages: (1) Vertically aligned structures reduce interconnect length, with correspondingly reduced power consumption and device footprint. (2) High mobility III-V materials boost the performance of the MOSFET itself [1]- [6]. Furthermore, (3) it enables functional scaling through heterogeneous material/device integration, such as MOSFET and imager, MicroLED, RF device, etc [5]- [10].…”

Section: Introductionmentioning

confidence: 99%

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

IEEE J. Electron Devices Soc.

Shin

et al. 2019

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Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%-30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.