Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III–V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (αp/αd = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics.

No abstract

A vertical bi-stable resistor (biristor) composed of In 0.53 Ga 0.47 As was demonstrated for sub-1 V operation. An inherent small bandgap and a scaled base length of 150 nm led to the remarkable reduction in latchup voltage compared to Si(Ge)-based conventional biristors. The epitaxially grown n-p-n structure allowed an abrupt p-n junction, which was also very important to reduce the latchup voltage. Furthermore, the physical mechanism of carrier transport in the InGaAs biristor was explored with TCAD simulations.Index Terms-3-D integration, abrupt junction artificial neural network, epitaxial growth, impact ionization, InGaAs, vertical biristor. I. INTRODUCTIONA LTHOUGH the capacitor-less one-transistor dynamic random-access memory (1T-DRAM) has shown great potential of being able to replace conventional DRAM with a higher packing density beyond 4F 2 , its three-terminal structure suffers from inherent gate reliability issues, such as hot carrier injection. [1], [2] To mitigate these issues, the bistable-resistor abbreviated as "biristor", has been developed. A biristor is an open-based two-channel bipolar junction transistor with a collector-base-emitter structure with a doping profile of either n + -p-n + or p + -n-p + . Biristors have shown promising characteristics with enhanced endurance and reliability for post-DRAM technology applications thanks to their gate-less operation. [3]-[6] Compared to 1T-DRAM, another attractive aspect of biristors is their potential for further cell size reduction thanks to their gate-less structure. In principle, when a biristor is formed vertically, the packing density can be reduced to be as small

No abstract