Heterogeneous memory management for embedded systems

Avissar, Oren; Barua, Rajeev; Stewart, Dave

doi:10.1145/502217.502223

Cited by 50 publications

(39 citation statements)

References 8 publications

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“…We do not directly exploit cache memories, but focus on scratch pad memories. These software controlled memories do not require complex tag-decoding logic [5]. Therefore, they have a lower energy cost per access compared to caches, and also reduce the indeterminacy of the system.…”

Section: Target Architecturementioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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Section: Target Architecturementioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

View full text Add to dashboard Cite

show abstract

“…We do not directly exploit caches, but focus on scratchpad memories. These software-controlled memories do not require complex tag-decoding logic [10,14]. Therefore, they have a lower energy cost per access compared to caches and also reduce the indeterminacy of the system.…”

Section: Target Architecturementioning

confidence: 99%

“…In the context of embedded systems, only a few techniques decide where to store the data at runtime taking the memory architecture into account For instance, [14,59] decide at the design time for each call-site to malloc=new to which memory the data should be assigned. They base their decision on simple criteria; object colocation to avoid conflict misses, object size and access frequency.…”

Section: Runtime Policiesmentioning

confidence: 99%

Power aware data and memory management for dynamic applications

Marchal

Perez

Atienza

et al. 2005

IEE Proc., Comput. Digit. Tech.

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads into account and do not deal with the dynamic behaviour of these novel applications. The main limitations of current techniques are outlined and an approach for dealing with them is introduced. Design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [1]. These systems require an enormous computational performance: 40 gigaoperations per second (GOPS). Even though current PCs could provide sufficient performance, they are too powerhungry (10 -100 W). Mobile devices should consume at least two or three orders of magnitude less [2]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently, and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. Era of platform-based designA platform is a fixed microarchitecture together with a programming environment that minimises mask-making costs and is flexible enough to work for a set of applications [3]. The production volumes can then remain high over an extended chip lifetime.To cope with the energy constraints, platforms usually consist of multiple processors. Since power is cubic to the processing frequency, parallelism is an effective way to reduce it. Therefore, on most platforms two or more processors are integrated. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a digital signal processor (DSP). The RISC is more energy-efficient for the input=output processing and control-dominated applications. The DSP, however, provides the computational performance for audio and video processing, while keeping the energy cost bounded. Indeed, taking a look to the current market offers (e.g. ST Nomadik

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“…Other proposals exist in the literature that use small buffers to increase performance or decrease power consumption ( [21][3] [2] [25] among others). However, none of them are targeted to deal with the wire delay problem in a clustered environment and do not provide the flexibility offered by the buffers proposed in this paper.…”

Section: Related Workmentioning

confidence: 99%

“…Assume the next piece of code, where a and b are 2-byte element arrays: [2] ... will continuously be mapped to cluster 3's L0 buffer. However, it has been observed that unrolling a loop N times (being N the number of clusters) helps to balance the workload of instructions among clusters and performance is often improved [22].…”

Section: Mapping Flexibilitymentioning

confidence: 99%