Heterogeneous multicore SDRAM interference analysis

Abstract

The purpose of this paper is to describe a set of DDR3 SDRAM interference estimation cost functions. The arbitration system of the SDRAM controller heavily impact the interference analysis. In this work, three arbitration are considered, corresponding to the situations where the accessed memory address belongs to the same block address, different memory banks and different rows. The aim of these functions is to estimate the instructions interference overhead may suffer when concurrently accessing these three logical addresses in a SDRAM saturation context. To develop these interference expressions, specific measurement systems, microbenchmarks and theory on SDRAM controllers have been used. CCS CONCEPTS• Computer systems organization → Real-time system architecture; Real-time system specification; Real-time system architecture.

Towards an efficient cost function equation for DDR SDRAM interference analysis on heterogeneous MPSoCs

“…The oldest commands have priority. The quantified effects of the arbitration logic can be seen in [10]. In terms of commands priority, the controller follows a Column-First scheduling policy where RD and WR commands (column accesses) are prioritized over ACT and PRE commands (row accesses).…”