Heterojunction fully depleted SOI-TFET with oxide/source overlap

Electrical noise in Circular Gate Tunnel FET in presence of interface traps

“…Various geometries and structural modifications of TFETs have been proposed in order to improve the on-current. These include Double Gate TFET (DG TFET) [7,8], Silicon-on-Insulator TFET (SOI) [9][10][11][12], Hetero-Gate Dielectric TFET (HG TFET) [13], Dual Material Gate TFET (DMG TFET) [14] and bandgap engineered TFET [15].…”

Performance Evaluation of Epitaxial Layer Based Gate Modulated TFET (GM-TFET)

“…One of the foremost disadvantage of TFET is its low ON state current [4][5]. Various research have been presented through structural engineering to enhanced the ON current of TFET like silicon on insulator (SOI) TFET [6], heterojunction TFET (HJ-TFET) [7], circular gate TFET (CG-TFET) [8], double gate (DG) TFET [9], dual material gate (DMG) TFET [10] and many more. Also, epitaxial layer (ETL) based TFET architecture is proposed to make TFET suitable for low power applications [11][12].…”

Research on Total Ionizing Dose Effect and Reinforcement of SOI-TFET

“…This paper focuses on the TID effect in SOI-TFET with oxide/source overlap, the structure of the device is described in Figure 1 . The gate of the device overlaps the oxide and the source can increase the on-state current [ 10 , 11 , 12 ], while the SOI structure can eliminate the latch-up effect and reduce parasitic capacitance [ 13 , 14 , 15 , 16 ]. It is found that the current switch ratio and subthreshold swing of the device deteriorates while threshold voltage has a slight drop, but it is not too sensitive after irradiation.…”