Heuristic minimization of BDDs using don't cares

Shiple, Thomas R.; Hojati, Ramin; Sangiovanni‐Vincentelli, Alberto; Brayton, Robert K.

doi:10.1145/196244.196360

Cited by 78 publications

(43 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Section: Don't Care Optimizationmentioning

confidence: 99%

“…Several heuristics to minimize BDD size using don't cares are presented in [20]. Since the area of a decomposed BDD-based PTL circuit is proportional to the BDD size, the results of [20] can be applied to PTL synthesis directly. The synthesis algorithm would then be modified as follows: after generating the decomposed BDD representation, we minimize the target function BDD and each decomposition point BDD travelling from the primary outputs of the circuit to primary inputs.…”

Section: Don't Care Optimizationmentioning

confidence: 99%

“…The don't care set construction is the same as in the case of the multi-level network minimization and we refer the reader to [18] for more details. The heuristics of [20] are then applied to minimize the BDD. Based on the results reported in [20], we expect this extension to yield significant reduction in the area of the PTL circuits.…”

Section: Don't Care Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

View full text Add to dashboard Cite

show abstract

Section: Don't Care Optimizationmentioning

confidence: 99%

Section: Don't Care Optimizationmentioning

confidence: 99%

Section: Don't Care Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

View full text Add to dashboard Cite

show abstract

“…This RODG operator can be used to obtain a more compact RODG representation for an incompletely specified function. The restrict operator belongs to a family of heuristics (Shiple et al, 1994) that generate a small RODG by merging, in a bottom-up fashion, nodes in an RODG. The merging of nodes is performed in a way that keeps the RODG consistent with the training set data.…”

Section: Initialization Using the Restrict Operatormentioning

confidence: 99%

“…Variations on this method and a complete analysis of alternative methods to chose mergings are analyzed in depth by Shiple (1994).…”

Section: Initialization Using the Restrict Operatormentioning

confidence: 99%

Using the minimum description length principle to infer reduced ordered decision graphs

Oliveira

Sangiovanni‐Vincentelli

1996

Mach Learn

View full text Add to dashboard Cite

Abstract.We propose an algorithm for the inference of decision graphs from a set of labeled instances. In particular, we propose to infer decision graphs where the variables can only be tested in accordance with a given order and no redundant nodes exist. This type of graphs, reduced ordered decision graphs, can be used as canonical representations of Boolean functions and can be manipulated using algorithms developed for that purpose. This work proposes a local optimization algorithm that generates compact decision graphs by performing local changes in an existing graph until a minimum is reached. The algorithm uses Rissanen's minimum description length principle to control the tradeoffbetween accuracy in the training set and complexity of the description. Techniques for the selection of the initial decision graph and for the selection of an appropriate ordering of the variables are also presented. Experimental results obtained using this algorithm in two sets of examples are presented and analyzed.

show abstract

Using XBDDs and ZBDDs in points‐to analysis

Lhoták¹,

Curial²,

Amaral³

2008

Softw Pract Exp

View full text Add to dashboard Cite

Binary decision diagrams (BDDs) have recently become widely accepted as a space‐efficient method of representing relations in points‐to or reference analyses. When BDDs are used to represent relations, each element of a domain is assigned a bit pattern to represent it, but not every bit pattern represents an element. The circuit design, model checking, and verification communities have achieved significant reductions in BDD sizes using several techniques to reduce the overhead of these don't‐care bit patterns. We adapt these techniques to BDD‐based program analysis, and we study their effect on the BDD size in this context. Specifically, we compare the effectiveness of Coudert and Madre's restrict operation and the use of zero‐suppressed BDDs (ZBDDs) to represent relations. Using don't‐care BDDs (XBDDs) and ZBDDs to reduce the size of the relations allows a compiler or other software analysis tools to analyze larger programs with greater precision. Our experimental evaluation considers both context‐insensitive and context‐sensitive program analyses. We also provide a metric that can be used to estimate whether ZBDDs will be more compact than BDDs for a given analysis. Copyright © 2008 John Wiley & Sons, Ltd.

show abstract

Heuristic minimization of BDDs using don't cares

Cited by 78 publications

References 7 publications

Logic synthesis for large pass transistor circuits

Logic synthesis for large pass transistor circuits

Using the minimum description length principle to infer reduced ordered decision graphs

Using XBDDs and ZBDDs in points‐to analysis

Contact Info

Product

Resources

About