Logic synthesis for large pass transistor circuits

Buch,; Narayan,; Newton,; Sangiovanni-Vincentelli, A.

doi:10.1109/iccad.1997.643609

Cited by 71 publications

(85 citation statements)

References 20 publications

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“…To compare results on equal footing, we have translated our results to the corresponding parameters reported in those works and compared our results. Table 2 compares our result with that of [2], where percentage reductions in area and delay with respect to static CMOS circuits have been reported without specifying exact values. In Columns 2 and 3 of Table 2, percentage reduction in area and delay in PTL based circuits with respect to static CMOS circuits as reported in [2] are presented.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 91%

“…When the network is implemented using nMOS transistor only, then it uses more number of transistors than the implementation using nMOS-pMOS transistors, because it needs signal in both the input phases for each binary node. However, it produces good results in terms of gate areas [2]. Implementation of only nMOS network has one major limitation; the voltage is V DD -V T for output "1" and V SS for output "0".…”

Section: Mapping a Bdd To Ptl Circuitmentioning

confidence: 99%

“…As the size of BDDs is more important than the same ordering of variables through different paths, we have adopted this new approach. Efficacy of this heuristic has been established by comparing the sizes of BDDs obtained using our approach with those works reported in [2], [3] and [4].…”

Section: Introductionmentioning

confidence: 99%

“…The size of the monolithic BDDs grow exponentially with the number of input variables of the functions, making the approach unsuitable for functions of large number of variables, which is common in presentday VLSI circuits. Decomposed-BDD approach [2] has been proposed to overcome this problem. In decomposed-BDD approach, instead of creating a single big monolithic BDD, compact BDDs in terms of intermediate variables are constructed.…”

Section: Introductionmentioning

confidence: 99%

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Synthesis of high performance low power PTL circuits

Samanta

Dharmadeep

Pal

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-Among the various CMOS logic families, PTL has been recognized as one of the potential alternatives to static CMOS for the synthesis of high performance and low power circuits. Moreover, as BDDs can be readily mapped to PTL circuits, use of BDDs has been synonymous with the synthesis of PTL circuits. Most of the reported works on PTL synthesis are based on the Reduced Ordered BDDs (ROBDDs). We have developed a novel heuristic-based technique for obtaining Reduced Unordered BDDs (RUBDDs), which leads to circuits of smaller size having lesser delay and smaller power consumption compared to the existing results. We propose the technology mapping using the popular LEAP-like cells, such that the PTL circuit synthesis flow has the same flavor as that of the standard cell-based static CMOS circuit synthesis. We have also developed models for the estimation of delay and power consumption of the synthesized PTL circuits and compared those with the static CMOS and other existing PTL-based circuit realizations. I IntroductionIn recent years, static CMOS has emerged as the technology of choice for VLSI circuit realization, because of the ease of design, robustness, scalability and other advantages that this logic style offers. But, static CMOS uses both pMOS and nMOS transistor networks, taking larger area, incurring more delay and higher power dissipation. As a consequence, in the present era of sub-micron technology, driven by the need for low power and high performance, researchers are looking for better alternatives. Recent studies [1]- [4] show that pass transistor logic (PTL) circuits provide superior performance in terms of area, delay and power. However, PTL circuits have some inherent limitations, such as threshold voltage drop across pass transistors, possibility of sneak paths and higher delay for cascaded pass transistors. While synthesizing PTL circuits, care should be taken to overcome these limitations.Although PTL is a promising alternative to static CMOS, it demands for a radically different logic synthesis approach. It has been observed that binary decision diagram (BDD) representation of a logic function can be readily mapped onto a PTL network. Moreover, BDD-based synthesis avoids some of the limitations mentioned above. This has made BDD-based approach very attractive for the synthesis of PTL circuits. In earlier works In this paper, we have also used decomposed BDDs for PTL circuits synthesis. In addition to using decomposed BDDs, we have used a new heuristic, based on ratio parameters (RP), for optimal variable ordering. The concept of RP was used earlier [6], [7] for the synthesis of multiplexer-based circuits. The RP-based heuristic helps in obtaining BDDs with smaller number of nodes. However, BDDs generated by this approach may not have the same ordering of variables at the same level along different paths. These BDDs may be termed as Reduced Unordered BDDs (RUBDDs), in contrast to Reduced Ordered BDDs (ROBDDs) commonly used in the existing approaches. As the size of BDDs is more importan...

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Section: Implementation and Experimental Resultsmentioning

confidence: 91%

Section: Mapping a Bdd To Ptl Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Synthesis of high performance low power PTL circuits

Samanta

Dharmadeep

Pal

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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“…A number of approaches have also been developed which explore the structure of the decision diagram representation of a given function [85,77,86,87]. The close relation between BDDs and multiplexer circuits has also lead to several approaches to synthesis of pass transistor logic (PTL) [88,89,76,90]. They are primarily based on a mapping of (decomposed) BDDs to PTL.…”

Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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