HEVC Deblocking Filter

Norkin, Andrey; Bjøntegaard, Gisle; Fuldseth, Arild; Narroschke, Matthias; Ikeda, Masaru; Andersson, Kristoffer; Zhou, Minhua; Auwera, Geert Van Der

doi:10.1109/tcsvt.2012.2223053

Cited by 307 publications

(143 citation statements)

References 2 publications

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“…The working frequency needed to support a specific video sequence can be calculated by equation (3). Here W is picture width and H is the picture height.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Fps is the frame rate. In order to support the target resolution (4096 × 2304@60 fps and 4 : 2 : 0 format), the working frequency is 60.8 MHz according to equation (3 …”

Section: Implementation Resultsmentioning

confidence: 99%

“…But the computational complexity of the deblocking filter is reduced. Only the 8 × 8 block boundaries which are also prediction unit boundaries or transform unit boundaries are filtered in HEVC [3].…”

Section: Introductionmentioning

confidence: 99%

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A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

Shen

Sui

Fan

et al. 2013

IEICE Electron. Express

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This paper present a high throughput design for Sample Adaptive offset (SAO) filter and deblocking filter used in an HEVC decoder. A five-stage pipelined architecture is proposed to support both SAO filter and deblocking filter on a 32 × 32 pixel block basis. Deblocking filter and SAO filter can work simultaneously in consecutive pipeline stages. The on-chip SRAM can also be shared by deblocking filter and SAO filter. Coupled with the novel filter order, an interlaced SRAM memory mapping scheme is proposed to increase the throughput for deblocking filter. The experimental results show that our design can support 4K × 2K@60 fps (4096 × 2304) HEVC video sequence at the working frequency of only 60.8 MHz.

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“…The working frequency needed to support a specific video sequence can be calculated by equation (3). Here W is picture width and H is the picture height.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Fps is the frame rate. In order to support the target resolution (4096 × 2304@60 fps and 4 : 2 : 0 format), the working frequency is 60.8 MHz according to equation (3 …”

Section: Implementation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

Shen

Sui

Fan

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…DBF helps to improve video quality by removing blocking artifacts and discontinuities introduced into the frames due to coarse quantization. The DBF filter is applied across 8 × 8 sample blocks in HEVC, whereas, in H.264, 4 × 4 sample blocks are filtered [3]. The computational complexity of the deblocking filter in HEVC is less than that of the H.264.…”

Section: High Efficiency Video Coding (Hevc) Is the New Video Codingmentioning

confidence: 99%

FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications

Khan¹,

Raja²

2016

Turk J Elec Eng & Comp Sci

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This paper proposes the architecture of a deblocking filter (DBF) that removes blocking artifacts in new emerging High Efficiency Video Coding (HEVC). A parallel architecture for both normal and strong filtering modes of HEVC is proposed. Distributed memories and two data paths increase the parallelism and make the architecture more efficient. The proposed architecture is described by Verilog and implemented on FPGA. The architecture can realize real time to compute 4K UHD video at 30 fps by using 46.65 million clocks with total equivalent gate count of 46K. The maximum delay time for output to come after taking input for the proposed architecture is 18.514 ns and the currently operating frequency is 54 MHz.

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“…In terms of entropy coding, HEVC abandoned the H.264 context-based adaptive-variable length coding (CAVLC) but retained the more efficient Context-based Adaptive-binary Arithmetic Coding (CABAC) method, in addition to optimizing the speed and compression rate as well as the context of the storage [5]. With regard to the deblocking filter, HEVC and H.264 are similar, but HEVC uses an 8 × 8 sampling grid, which is more suitable for parallel operation [6]. Parallel processing architecture is one of the advantages of HEVC.…”

Section: Introductionmentioning

confidence: 99%

A novel architecture for parallel multi-view HEVC decoder on mobile device

Liu

Cho

2017

J Image Video Proc.

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The multi-view HEVC (MV-HEVC) extension was finalized in July of 2014 by the Moving Picture Experts Group and the Video Coding Experts Group. Recently, multi-view videos based on stereo representations are becoming widely popular. Also, a variety of multimedia contents are now available for mobile devices. A real-time multi-view video decoder is therefore needed. In mobile devices, a real-time decoding multi-view video is difficult because of the increasing number of views, spatial resolutions, and limited speed of the processors on mobile platforms. In this paper, we propose a novel architecture for a real-time decoder in mobile devices. The proposed MV-HEVC decoder uses parallel-optimized multi-view video decoding with multi-threading, using advanced reduced instruction set computer machine (ARM) Cortex multi-core processors. Moreover, it is optimized in single instruction multiple data for an ARM platform. The proposed multi-core decoding architectures enable multi-threading with minimum processing overhead. Experimental results show that the proposed multi-view video coding increased the speed by around 2.4-4.8 times in the ARM platform compared to MV-HEVC.

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HEVC Deblocking Filter

Cited by 307 publications

References 2 publications

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC

FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications

A novel architecture for parallel multi-view HEVC decoder on mobile device

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