HEVC performance and complexity for 4K video

Bross, Benjamin; George, Valeri; Alvarez-Mesa, Mauricio; Mayer, Tobias; Ching, Chi Bun; Brandenburg, Jens; Schierl, Thomas; Marpe, Detlev; Juurlink, Ben

doi:10.1109/icce-berlin.2013.6698051

Cited by 9 publications

(3 citation statements)

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“…11,12 In addition, studies regarding the HEVC software decoding performance and complexity for high resolution sequences have been also performed. 13 As already noted in the introduction, the inter-picture prediction in HEVC relies on MVs with quarter sample accuracy similarly to the inter-picture prediction in H.264/MPEG-4 AVC. However, for the MVP derivation, the median based predictor using spatially neighboring MVs was replaced by a competitive scheme, which is applied on a set of candidates derived from both spatial and temporal neighboring MVs.…”

Section: Background and Related Workmentioning

confidence: 94%

Pattern-based integer sample motion search strategies in the context of HEVC

Maier

Bross

Grois³

et al. 2015

SPIE Proceedings

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The H.265/MPEG-H High Efficiency Video Coding (HEVC) standard provides a significant increase in coding efficiency compared to its predecessor, the H.264/MPEG-4 Advanced Video Coding (AVC) standard, which however comes at the cost of a high computational burden for a compliant encoder. Motion estimation (ME), which is a part of the inter-picture prediction process, typically consumes a high amount of computational resources, while significantly increasing the coding efficiency. In spite of the fact that both H.265/MPEG-H HEVC and H.264/MPEG-4 AVC standards allow processing motion information on a fractional sample level, the motion search algorithms based on the integer sample level remain to be an integral part of ME. In this paper, a flexible integer sample ME framework is proposed, thereby allowing to trade off significant reduction of ME computation time versus coding efficiency penalty in terms of bit rate overhead. As a result, through extensive experimentation, an integer sample ME algorithm that provides a good trade-off is derived, incorporating a combination and optimization of known predictive, pattern-based and early termination techniques. The proposed ME framework is implemented on a basis of the HEVC Test Model (HM) reference software, further being compared to the state-of-the-art fast search algorithm, which is a native part of HM. It is observed that for high resolution sequences, the integer sample ME process can be speed-up by factors varying from 3.2 to 7.6, resulting in the bit-rate overhead of 1.5% and 0.6% for Random Access (RA) and Low Delay P (LDP) configurations, respectively. In addition, the similar speed-up is observed for sequences with mainly Computer-Generated Imagery (CGI) content while trading off the bit rate overhead of up to 5.2%

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Section: Background and Related Workmentioning

confidence: 94%

Pattern-based integer sample motion search strategies in the context of HEVC

Maier

Bross

Grois³

et al. 2015

SPIE Proceedings

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“…It has been demonstrated that by using SIMD and multithreading it is possible to achieve very high performance for HEVC decoding on recent computer architectures [Bossen et al 2012;Chi et al 2014;Bross et al 2013]. As a result, much higher than real-time frame rates can be achieved even for UHD resolution videos on commodity desktop and mobile processors.…”

Section: Introductionmentioning

confidence: 99%

Low-Power High-Efficiency Video Decoding using General-Purpose Processors

Ching

Alvarez-Mesa

Juurlink

2015

ACM Trans. Archit. Code Optim.

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Low power high efficiency video decoding using general purpose processors Article, Postprint versionThis version is available at http://dx.doi.org/10.14279/depositonce-6343 Suggested CitationChi, C. C.; Alvarez-Mesa, M.; Juurlink, B.: Low-Power High-Efficiency Video Decoding using General-Purpose Processors. In this paper we investigate how code optimization techniques and low power states of general purpose processors improve the power efficiency of HEVC decoding. The power and performance efficiency of the use of SIMD instructions, multicore architectures, and low power active and idle states are analyzed in detail for offline video decoding. In addition, the power efficiency of techniques such as "race to idle" and "exploiting slack" with DVFS are evaluated for real-time video decoding. Results show that "exploiting slack" is more power efficient t han " race t o i dle" f or a ll e valuated p latforms r epresenting s martphone, t ablet, l aptop and desktop computing systems.

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“…[15] shows that real-time decoding of 4K video with a frame-level parallel decoding approach using four desktop CPU cores is feasible.…”

Section: H265 Video Codecmentioning

confidence: 99%