HFNet: A CNN Architecture Co-designed for Neuromorphic Hardware With a Crossbar Array of Synapses

Abstract

The hardware-software co-optimization of neural network architectures is a field of research that emerged with the advent of commercial neuromorphic chips, such as the IBM TrueNorth and Intel Loihi. Development of simulation and automated mapping software tools in tandem with the design of neuromorphic hardware, whilst taking into consideration the hardware constraints, will play an increasingly significant role in deployment of system-level applications. This paper illustrates the importance and benefits of co-design of convolutional neural networks (CNN) that are to be mapped onto neuromorphic hardware with a crossbar array of synapses. Toward this end, we first study which convolution techniques are more hardware friendly and propose different mapping techniques for different convolutions. We show that, for a seven-layered CNN, our proposed mapping technique can reduce the number of cores used by 4.9-13.8 times for crossbar sizes ranging from 128 × 256 to 1,024 × 1,024, and this can be compared to the toeplitz method of mapping. We next develop an iterative co-design process for the systematic design of more hardware-friendly CNNs whilst considering hardware constraints, such as core sizes. A python wrapper, developed for the mapping process, is also useful for validating hardware design and studies on traffic volume and energy consumption. Finally, a new neural network dubbed HFNet is proposed using the above co-design process; it achieves a classification accuracy of 71.3% on the IMAGENET dataset (comparable to the VGG-16) but uses 11 times less cores for neuromorphic hardware with core size of 1,024 × 1,024. We also modified the HFNet to fit onto different core sizes and report on the corresponding classification accuracies. Various aspects of the paper are patent pending.

A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits

“…The architecture seen in Fig. 2 [31] works well for binarized synapses. However, if multilevel weights (using MLC cells) are employed, then the device resistances drift over time and the variance of the MLC states increases with time (on the order of hours to days) and temperature [25], [32].…”

“…However, this assumes that the spikes are sparse and ignores AER collisions and the need for asynchronous buffers which are complex to implement. A fully parallel realization of CNN has recently been attempted where the inputs are 'unrolled' and mapped to larger RRAM array(s) [19], [30], [31]. In a simple block-based scheme, convolution operation with…”

“…A single N x N y ×N x N y array can be used for implementing each feature map. Larger features can be split into smaller arrays and their outputs are stitched together [31]. For example, the first CNN layer in Fig.…”

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

“…DFSynthesizer is designed for crossbar-based neuromorphic hardware designs as shown in Figure 2. This is representative of many recent neuromorphic designs [3,25,56,61]. A machine learning model (ANN or SNN) is irst analyzed to generate its workload (Section 3).…”

“…Our system architecture, integrating a neuromorphic hardware. DFSynthesizer is designed for crossbar-based neuromorphic hardware [3,25,56,61]. This is representative of many recent neuromorphic designs.…”