HfO<sub>2</sub>-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

Saitoh, Masumi; Ichihara, Reika; Yamaguchi, Mari; Suzuki, K.; Takano, Keisuke; Akari, Keisuke; Takahashi, Kyoko; Kamiya, Yuta; Matsuo, Kazuhiro; Kamimuta, Yuuichi; Sakuma, Kiwamu; Ota, Ken‐ichiro; Fujii, Shosuke

doi:10.1109/iedm13553.2020.9372106

Cited by 28 publications

(16 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…11. Drift of both high-and low-VTH are in general non-symmetric [22], [93], [98], and depend on the sign of charged traps (i.e., either positive or negative depending on whether holes or electrons are trapped) [73], [74], [97], [99], on the local field induced by ferroelectric polarization [100], as well as on the doping of the semiconductor substrate [101]. Moreover, the type of stress sequence applied during endurance tests, i.e., either bipolar or unipolar stress, determines different degree of asymmetric degradation [22], [79], [93], also as a consequence of charge injection into traps facilitated by the internal fields induced by the ferroelectric polarization [22].…”

Section: B Endurancementioning

confidence: 99%

“…14(a). In addition, the evolution over time of MW (which influences endurance) is determined by the compensation rate of polarization by the parasitic Qcomp [93], [98]. We stress on the fact that the trend lines in Fig.…”

Section: Trade-offs Among the Metricsmentioning

confidence: 99%

“…The analytical formulation therefore relies on the knowledge about the IL degradation mechanisms and can be adapted for different FeFET gate stacks and transistor geometries. Ichihara et al modeled degradation as a concurrent effect of Ps reduction and increase of polarization screening by charged traps with cycling, concluding that reduction of charging/dis-charging of IL traps is key to improve endurance [93], [98].…”

Section: Endurance Degradationmentioning

confidence: 99%

See 2 more Smart Citations

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

2023

View full text Add to dashboard Cite

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, high-speed, and lowpower operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. There is a broad consensus that a deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this paper, we review the current understanding of the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at device-level (i.e., retention, endurance, variability) based on the physical mechanisms previously identified. Our integrative theoretical framework connects apparently unrelated reliability issues and suggests mitigation strategies at either device, circuit, and system level. We conclude the paper by proposing a set of research opportunities to guide future development in this field.

show abstract

Section: B Endurancementioning

confidence: 99%

Section: Trade-offs Among the Metricsmentioning

confidence: 99%

Section: Endurance Degradationmentioning

confidence: 99%

See 1 more Smart Citation

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

2023

View full text Add to dashboard Cite

show abstract

“…[15] The factors which limit the endurance of a FeFET are concluded to be the charge trapping phenomenon caused by the spontaneous polarization. [16][17][18][19] To improve the endurance of the FeFET, it is important to understand the mechanism of charge trapping. However, the current method of characterizing the phenomenon of charge trapping through experimental measurement still cannot clarify the driving force.…”

Section: Introductionmentioning

confidence: 99%

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

Sun

Chai

et al. 2023

Chinese Phys. B

View full text Add to dashboard Cite

In this work, we study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with Metal/Ferroelectric/Interlayer/Si (MFIS)gate stack structure. In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect, we first establish a model to simulate the electron trapping behavior in n-type Si FeFET. The model is based on the quantum mechanical electron tunneling theory. And then, we use the pulsed I d -V g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET. Our model fits the experimental data well. By fitting the model with the experimental data, we get the following conclusions: (1) During the positive operation pulse, electrons in the Si substrate are mainly trapped at the interface between the ferroelectric (FE) layer and interlayer (IL) of the FeFET gate stack by inelastic trap-assisted tunneling; (2) Based on our model, we can get the number of electrons trapped into the gate stack during the positive operation pulse; (3) The model can be used to evaluate trap parameters, which will help us to further understand the fatigue mechanism of FeFET.

show abstract

“…FEFET technology faces a critical challenge with respect to its write voltage, i.e., the voltage required to switch ferroelectric polarization in the FEFET structure. State-of-the art, Si-based FEFETs require at least 3–6 V for deterministic switching. − Conversely, for compatibility with logic circuits in embedded applications, the write voltage needs to be decreased below 1.5 V . This challenge arises in part because during the deposition of the ferroelectric layer on Si in the standard transistor fabrication processes, an interfacial SiO 2 layer forms.…”

Section: Introductionmentioning

confidence: 99%

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures

Tasneem

Kashyap

Chae

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Discovery of ferroelectricity in HfO2 has sparked a lot of interest in its use in memory and logic due to its CMOS compatibility and scalability. Devices that use ferroelectric HfO2 are being investigated; for example, the ferroelectric field-effect transistor (FEFET) is one of the leading candidates for next generation memory technology, due to its area, energy efficiency and fast operation. In an FEFET, a ferroelectric layer is deposited on Si, with an SiO2 layer of ∼1 nm thickness inevitably forming at the interface. This interfacial layer (IL) increases the gate voltage required to switch the polarization and write into the memory device, thereby increasing the energy required to operate FEFETs, and makes the technology incompatible with logic circuits. In this work, it is shown that a Pt/Ti/thin TiN gate electrode in a ferroelectric Hf0.5Zr0.5O2 based metal-oxide-semiconductor (MOS) structure can remotely scavenge oxygen from the IL, thinning it down to ∼0.5 nm. This IL reduction significantly reduces the ferroelectric polarization switching voltage with a ∼2× concomitant increase in the remnant polarization and a ∼3× increase in the abruptness of polarization switching consistent with density functional theory (DFT) calculations modeling the role of the IL layer in the gate stack electrostatics. The large increase in remnant polarization and abruptness of polarization switching are consistent with the oxygen diffusion in the scavenging process reducing oxygen vacancies in the HZO layer, thereby depinning the polarization of some of the HZO grains.

show abstract

HfO₂-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

Cited by 28 publications

References 2 publications

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures

Contact Info

Product

Resources

About

HfO2-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

Cited by 28 publications

References 2 publications

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures

Contact Info

Product

Resources

About

HfO₂-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Reliability of HfO₂-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges