HiBRID-SoC: a multi-core architecture for image and video applications

Berekovic, Mladen; Flugel, S.; Stolberg, H.-J.; Friebe, L.; Moch, S.; Kulaczewski, M.B.; Pirsch, P.

doi:10.1109/icip.2003.1247191

Cited by 8 publications

(2 citation statements)

References 7 publications

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“…This is improved in dedicated encoding architectures [7], which means also limited programmability. Many architectures are neither purely dedicated nor programmable but combine the best of both approaches by utilizing co-processors that accelerate regular and computation-intensive tasks [8][9][10][11]. For portable devices, programmability is often sacrificed for other design requirements.…”

Section: Introductionmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

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Section: Introductionmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…The D30V [6] uses a basic dual-issue RISC architecture with instruction coded as VLIW for multimedia signal processing. Heterogeneous multiprocessor is used when there are parts of the embedded software that would need the power of digital signal processor and other parts need a micro-controller for the housekeeping activity, such as OMAP [7], VIPER [8], and HIBRID-SOC [9]. Ishiwata et.al [10] have developed a customizable media embedded processor architecture for digital media processing.…”

Section: Introductionmentioning

confidence: 99%

System-on-chip architecture with media DSP and RISC core for media application

Liu

2006

SPIE Proceedings

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Systems-on-chips provide single-chip solutions in many embedded applications to meet the applications size and power requirements. Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. The MediaSoC322xA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with the processor cores. The MediaSoC322xA is fabricated in a 0.18um 6LM standard-cell SMIC CMOS technology, occupies about 20mm 2 , and operates at 180MHz. The MeidaSoC322xA are used to audio/video decoder for embedded multimedia application. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx SPIE-IS&T/ Vol. 6074 60740D-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Design Methodology for Embedded Computer Vision Systems

Bhattacharyya

Saha

2009

Embedded Computer Vision

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Computer vision has emerged as one of the most popular domains of embedded applications. Though various new powerful embedded platforms to support such applications have emerged in recent years, there is a distinct lack of efficient domain-specific synthesis techniques for optimized implementation of such systems. In this thesis, four different aspects that contribute to efficient design and synthesis of such systems are explored:(1) Graph Transformations: Dataflow modeling is widely used in digital signal processing (DSP) systems. However, support for dynamic behavior in such systems exists mainly at the modeling level and there is a lack of optimized synthesis techniques for these models. New transformation techniques for efficient system-on-chip (SoC) design methods are proposed and implemented for cyclo-static dataflow and its parameterized version (parameterized cyclo-static dataflow) -two powerful models that allow dynamic reconfigurability and phased behavior in DSP systems.

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HiBRID-SoC: a multi-core architecture for image and video applications

Cited by 8 publications

References 7 publications

Scalable Architecture for SoC Video Encoders

Scalable Architecture for SoC Video Encoders

System-on-chip architecture with media DSP and RISC core for media application

Design Methodology for Embedded Computer Vision Systems

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