Hiding the Long Latency of Persist Barriers Using Speculative Execution

Shin, Seunghee; Tuck, James; Solihin, Yan

doi:10.1145/3079856.3080240

Cited by 44 publications

(10 citation statements)

References 37 publications

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“…Workloads. Our workloads include several microbenchmarks and two recoverable applications, consistent with recent PM works [10,26,29,30,39,40]. As described in Table 2, our microbenchmarks involve operations on commonly used datastructures: map, set, queue, list and vector.…”

Section: Methodsmentioning

confidence: 94%

“…We choose PMDK as it is publicly available, regularly updated, Intel-supported and optimized for Intel's PM hardware. Moreover, PMDK (v1.4 or earlier) has been used for comparison by most earlier PM proposals [10,29,30,39,40]. We evaluate both PMDK v1.5 (released October 2018), which uses hybrid undo-redo logging techniques as well as PMDK v1.4, which primarily relies on undo-logging.…”

Section: Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Mod

Haria

Hill

Swift

2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Persistent Memory (PM) makes possible recoverable applications that can preserve application progress across system reboots and power failures. Actual recoverability requires careful ordering of cacheline flushes, currently done in two extreme ways. On one hand, expert programmers have reasoned deeply about consistency and durability to create applications centered on a single custom-crafted durable datastructure. On the other hand, less-expert programmers have used software transaction memory (STM) to make atomic one or more updates, albeit at a significant performance cost due largely to ordered log updates.In this work, we propose the middle ground of composable persistent datastructures called Minimally Ordered Durable datastructures (MOD). We prototype MOD as a library of C++ datastructures-currently, map, set, stack, queue and vectorthat often perform better than STM and yet are relatively easy to use. They allow multiple updates to one or more datastructures to be atomic with respect to failure. Moreover, we provide a recipe to create additional recoverable datastructures.MOD is motivated by our analysis of real Intel Optane PM hardware showing that allowing unordered, overlapping flushes significantly improves performance. MOD reduces ordering by adapting existing techniques for out-of-place updates (like shadow paging) with space-reducing structural sharing (from functional programming). MOD exposes a Basic interface for single updates and a Composition interface for atomically performing multiple updates. Relative to widely used Intel PMDK v1.5 STM, MOD improves map, set, stack, queue microbenchmark performance by 40%, and speeds up application benchmark performance by 38%.

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Section: Methodsmentioning

confidence: 94%

Section: Methodsmentioning

confidence: 99%

Mod

Haria

Hill

Swift

2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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“…Software Cache [36] implements a resizable cache to combine writebacks and reduce CLF. Hardware modifications in the cache hierarchy and new instructions [39,49] are also proposed to reduce the latency of CLF. Also, some cache designs use (relaxed) non-volatile memories [44,50,51], which naturally eliminates CLF.…”

Section: Related Workmentioning

confidence: 99%

Ribbon

Ren

Liu

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Cache line flushing (CLF) is a fundamental building block for programming persistent memory (PM). CLF is prevalent in PM-aware workloads to ensure crash consistency. It also imposes high overhead. Extensive works have explored persistency semantics and CLF policies, but few have looked into the CLF mechanism. This work aims to improve the performance of CLF mechanism based on the performance characterization of well-established workloads on real PM hardware. We reveal that the performance of CLF is highly sensitive to the concurrency of CLF and cache line status. We introduce Ribbon, a runtime system that improves the performance of CLF mechanism through concurrency control and proactive CLF. Ribbon detects CLF bottleneck in oversupplied and insufficient concurrency, and adapts accordingly. Ribbon also proactively transforms dirty or non-resident cache lines into clean resident status to reduce the latency of CLF. Furthermore, we investigate the cause for low dirtiness in flushed cache lines in in-memory database workloads. We provide cache line coalescing as an applicationspecific solution that achieves up to 33.3% (13.8% on average) improvement. Our evaluation of a variety of workloads in four configurations on PM shows that Ribbon achieves up to 49.8% improvement (14.8% on average) of the overall application performance. CCS CONCEPTS • Hardware → Emerging technologies; • Computer systems organization → Multicore architectures; • Software and its engineering → Concurrency control.

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“…Hardware logging techniques introduce hardware support to improve the performance of logging. In some instances, logs are generated by the CPU, and special hardware support accelerates log management after their creation (i.e., writing the logs back to PM and preserving correct ordering between logs and in-place updates) [6,8,18,23,26,38]. In other proposals, logging is offloaded to dedicated hardware altogether [7,19,20,31,37].…”

Section: Atomic Durabilitymentioning

confidence: 99%

Distributed Logless Atomic Durability with Persistent Memory

Gupta¹,

Daglis

Falsafi³

2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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Datacenter operators have started deploying Persistent Memory (PM), leveraging its combination of fast access and persistence for significant performance gains. A key challenge for PM-aware software is to maintain high performance while achieving atomic durability. The latter typically requires the use of logging, which introduces considerable overhead with additional CPU cycles, write traffic, and ordering requirements. In this paper, we exploit the data multiversioning inherent in the memory hierarchy to achieve atomic durability without logging. Our design, LAD, relies on persistent buffering space at the memory controllers (MCs)-already present in modern CPUs-to speculatively accumulate all of a transaction's updates before they are all atomically committed to PM. LAD employs an on-chip distributed commit protocol in hardware to manage the distributed speculative state each transaction accumulates across multiple MCs. We demonstrate that LAD is a practical design relying on modest hardware modifications to provide atomically durable transactions, while delivering up to 80% of ideal-i.e., PM-oblivious software's-performance. CCS CONCEPTS • Computer systems organization → Processors and memory architectures; • Information systems → Storage class memory; Phase change memory.

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Hiding the Long Latency of Persist Barriers Using Speculative Execution

Cited by 44 publications

References 37 publications

Mod

Mod

Ribbon

Distributed Logless Atomic Durability with Persistent Memory

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