Hierarchical Current-Density Verification in Arbitrarily Shaped Metallization Patternsof Analog Circuits

Jerke, Goeran; Lienig, Jens

doi:10.1109/tcad.2003.819899

Cited by 30 publications

(19 citation statements)

References 23 publications

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“…Time-to-failure models are used in conjunction with available functional load and design data to perform design verification and validation tasks, such as aging simulation for NBTI, HCI or TDDB (RelXpert [23], Eldo [24]) or current density verification [25], during the design phase. Additionally, preventive design measures must always be taken into consideration to account for insufficient reliability models, purely random errors or yet unknown failure mechanisms [9], [17].…”

Section: Requirementsmentioning

confidence: 99%

“…These currents are then used during the IC physical design phase to lay out all interconnects with the correct cross-section areas, and to connect to all terminal pins without causing current density violations. The compliance with these EM design rules is then verified in the final layout result, using approaches such as [25] …”

Section: A Electromigration Aware Design Flowmentioning

confidence: 99%

“…Metal1 wire width".) Second, the current densities in the physical layout were calculated with [25] and compared with the permitted values of j eff . Critical current density violations were confirmed for Design2, which did not validate for the new mission profile without further layout adjustments.…”

Section: Effective Design Rules Based On Mission Profilesmentioning

confidence: 99%

See 2 more Smart Citations

Mission profile aware IC design - A case study

Jerke¹,

Kahng²

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Consistent consideration of mission profiles throughout a supply chain is essential for the development of robust electronic components. Consideration of mission profiles is still mainly a manual task today despite rapidly decreasing robustness margins in modern automotive semiconductor technologies. Mission profile awareness aids the automation of robustness aware design by formalizing and partially automating the generation, transformation, propagation and usage of all component-specific functional loads and environmental conditions for design implementation and validation. In addition, it aids the development of electronic components in yet immature technologies or in technologies with tight parameter variation bounds. This paper introduces the general concept, requirements and context of mission profile aware design. The general design approach is presented along with key differences and enhancements to existing design approaches. A case study focusing on mission profile usage and electromigration failure avoidance is presented to demonstrate various aspects of mission profile aware design.

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Section: Requirementsmentioning

confidence: 99%

Section: A Electromigration Aware Design Flowmentioning

confidence: 99%

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Mission profile aware IC design - A case study

Jerke¹,

Kahng²

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…1. After floorplanning, placement and routing, a verification of current densities is performed in order to identify regions with excessive currentdensity stress [3]. The terminal current values required for a currentdensity calculation are obtained from a prior simulation of analogand mixed-signal circuits or a current estimation within digital circuits [3,6,10].…”

Section: Overviewmentioning

confidence: 99%

“…It utilizes layout-based current-density data for correct wire and via (array) sizing by using any available currentdensity calculation tool (e.g., [3,10]). In contrast to published solutions for post-route layout modification of power and ground nets (e.g., [13]), our approach is not restricted to single-layer manhattanstyle layouts and, hence, it is applicable to any type of nets, including analog and digital signal nets.…”

Section: Introductionmentioning

confidence: 99%

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

Jerke

Lienig²,

Scheible

2004

Proceedings of the 41st Annual Design Automation Conference

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The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated circuits. We present a new approach that addresses this electromigration issue by considering current density and inhomogeneous current-flow within arbitrarily shaped metallization patterns during physical design. Our proposed methodology is based on a post-route modification of critical layout structures that utilizes current-density data from a previously performed current-density verification. It is especially tailored to overcome the lack of current-flow consideration within existing routing tools. We also present experimental results obtained after successfully integrating our methodology into a commercial IC design flow.

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In situ fabrication of freestanding single‐walled carbon nanotube rope interconnection

Kim

Kang

Seo

et al. 2012

Physica Status Solidi (a)

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A single‐walled carbon nanotube rope interconnect is fabricated by utilizing dielectrophoresis and capillary condensation. The rope connects a pair of prefabricated cantilevers with good alignment and outstanding packing density. The diameter and resistance of the rope are readily controlled by adjusting the dielectrophoresis parameters such as applied voltage and frequency. The properties of the rope, including packing density, electron transport, and maximum current density, are investigated. The maximum current density of the rope is measured to be as high as 1 × 107 A/cm2 in vacuum.

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Hierarchical Current-Density Verification in Arbitrarily Shaped Metallization Patternsof Analog Circuits

Cited by 30 publications

References 23 publications

Mission profile aware IC design - A case study

Mission profile aware IC design - A case study

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

In situ fabrication of freestanding single‐walled carbon nanotube rope interconnection

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