Hierarchical Dataflow Model for efficient programming of clustered manycore processors

Hascoët, Julien; Desnos, Karol; Nezan, Jean-François; Dinechin, Benoît Dupont de

doi:10.1109/asap.2017.7995270

Cited by 13 publications

(9 citation statements)

References 11 publications

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“…For further developments, we may extend this work to support other block types such as conditional execution block which is characterized with variable periods. As well as future work , we may also adopt the hierarchical approach proposed in [16] to perform hierarchical Simulink applications mapping into multi-core architecture. We also aim to extend S-Preesm work-flow to support the optimal scheduler proposed by Rebaya et al [24].…”

Section: Discussionmentioning

confidence: 99%

“…This mechanism enables the description of the internal behavior of nodes with SDF subgraphs and ensures deadlock freeness between levels thanks to interfaces mechanism. Moreover, using IBSDF MoC allows us to benefit from recent researches such as [16] which exploit hierarchical behavior of IBSDF MoC to optimize code generation process and enhance performance on multi-core architectures.…”

Section: Introductionmentioning

confidence: 99%

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Translating Hierarchical Simulink Applications to Real-time multi-core Execution

Rebaya¹,

Desnos²,

Hasnaoui³

2020

ujeee

Self Cite

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Matlab & Simulink i s i s widely used as a defacto s tandard t o design i ndustrial applications, video coding & decoding, and s ignal processing applica-tions. However, with t he s pectacular i ncrease i n t he num-ber of the cores available i n hardware platforms over t hese l ast years, passing f rom Simulink t o m ulti-core execution becomes m ore and m ore complex. I n t his context, s everal researches are done t o t ake benefit f rom t he high degree of parallelism and t o perform m ulti-core programming of Simulink applications.In this paper, we present an automated method for transforming hierarchical Simulink applications to embedded parallel software implementation. Our method consists of using IBSDF (Interfaced based Synchronous Dataflow) as an intermediate representation to extract parallelism. Moreover, our approach permits preserving synchronous semantics and hierarchical behavior of the Simulink model. The model-based approach makes it possible to verify the key properties of the system at compile-time, such as deadlock freeness and memory boundedness. The method has been implemented as an extension of the rapid prototyping tool named Preesm. Experiments show that our proposal gives, as a transformation result, a schedulable IBSDF graph equivalent in size to the Simulink model and allows better multi-core implementation performance than Matlab&Simulink sequential execution.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Translating Hierarchical Simulink Applications to Real-time multi-core Execution

Rebaya¹,

Desnos²,

Hasnaoui³

2020

ujeee

Self Cite

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“…Due to the great success of big.LITTLE architectures [1], recent studies also address architecture limitations in clusterised many‐core systems. In [18], a technique for deploying hierarchical data flow graphs efficiently onto clustered many‐core processors is proposed to help retrieve data locality, which is crucial for high performances and power consumption. On and Hussin [19] analysed the impact that different many‐core clustering methods have on multiprocessing architectures.…”

Section: Literature Reviewmentioning

confidence: 99%

Exploiting memory allocations in clusterised many‐core architectures

Garibotti

Ost

Butko

et al. 2019

IET Computers & Digital Techniques

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Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterization is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e., memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterized many-core architectures. First, this work reviews the current literature on memory allocations and explore the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise, compared to the conventional centralized shared memory solution to reveal which memory allocation is the most appropriate for future mobile architectures. Our results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption.

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“…Dataflow programming provides the application programmer with a higher level of abstraction. Related work on dataflow programming techniques for manycore architectures focuses on either dynamic [18], [2], [17] or static [7], [14], [9] classes of dataflow MoCs. Reconfigurable dataflow MoC offer a tradeoff between dynamicity and predictability that can be exploited by a runtime manager to verify application properties or to perform optimizations at runtime, like the mapping of actor computations [10].…”

Section: Sobel Erosionmentioning

confidence: 99%

“…During the processing of each Tseq+Tpar ) −1 = 28. In [9], the authors evaluate the performance of a static version of the PiSDF graph from Figure 1. In the static version, N is fixed and all mapping and scheduling are done at compile time for VGA videos (640x480).…”

Section: ) Lrt Memory Footprintmentioning

confidence: 99%

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

Miomandre

Hascoët

Desnos

et al. 2018

Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Archite

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Embedded manycore architectures offer energyefficient super-computing capabilities but are notoriously difficult to program with traditional parallel Application Programming Interfaces (APIs). To address this challenge, dataflow Models of Computation (MoCs) are increasingly used as their high-level of abstraction eases the automation of computation mapping, memory allocation, and communication management. Reconfigurable dataflow is a class of dataflow MoC that fosters a unique tradeoff between application dynamicity and predictability. This paper introduces the first embedded runtime manager enabling the execution of reconfigurable dataflow graphs on a Non-Uniform Memory Access (NUMA) architecture. The proposed runtime manager dynamically deploys reconfigurable dataflow graphs on clustered Processing Elements (PEs) through the Networkson-Chips (NoCs) of the manycore architecture. An open-source implementation on the Kalray MPPA R processor demonstrates the feasibility and the great potential of such a runtime. The first results with an image processing application show a power efficiency 2.5 times better than on a multicore x86 architecture.

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Hierarchical Dataflow Model for efficient programming of clustered manycore processors

Cited by 13 publications

References 11 publications

Translating Hierarchical Simulink Applications to Real-time multi-core Execution

Translating Hierarchical Simulink Applications to Real-time multi-core Execution

Exploiting memory allocations in clusterised many‐core architectures

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures

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