Hierarchical defect-oriented fault simulation for digital circuits

Blyzniuk, M.; Cibakova, T.; Gramatova, Elena; Kuźmicz, Wiesław; Lobur, Mykhaylo; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund

doi:10.1109/etw.2000.873781

Cited by 17 publications

(8 citation statements)

References 10 publications

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“…Such estimation allows to improve the work on the development and generation of test cycles and to provide high quality of tests [12,14,15]. The high quality of the test and improvement of work of the test developers is provided by finding the best sequence of patterns for the detection of all faults and by reducing the average length of the sequence of patterns to a minimum as it shown in Fig.…”

Section: Usefulness Of Patterns In Defects Detectingmentioning

confidence: 99%

Reliability-aimed defect/fault characterization of standard cells of VLSI circuits

Blyzniuk¹,

Vanzeveren

2008

2008 26th International Conference on Microelectronics

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In given paper the approach for increasing reliability of VLSI circuits by probabilistic-based defect/fault characterization of standard cells is considered. Proposed approach is based on careful defect/fault analysis of complex gates from industrial cell library. Cell characterization includes probabilistic analysis of physical defects (including latent defects), identification of complex gates realistic faulty function caused by probable defects, determination of testability and development of recommendations for layout improvement aimed at decreasing of design sensitivity to physical defects.

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Section: Usefulness Of Patterns In Defects Detectingmentioning

confidence: 99%

Reliability-aimed defect/fault characterization of standard cells of VLSI circuits

Blyzniuk¹,

Vanzeveren

2008

2008 26th International Conference on Microelectronics

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“…The PCbased tools installed locally and Java applets invoked remotely via Internet supplement each other and form the engine of the whole concept. The PC-based tool set is called Turbo Tester (TT) [1,7] and consists of the following main tools: test generators based on various algorithms, logic and fault simulators, a test optimizer, a module for hazard analysis [6], a simulator and test generator for defects [2], built-in self-test simulators [4], design verification and design error diagnosis tools [5]. This range of compatible diagnostic tools forms, via their interaction and complementary operation, a homogeneous research environment, which provides good possibilities for laboratory training and experimental research.…”

Section: Introductionmentioning

confidence: 99%

Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems

Jutman¹,

Ubar²,

Wuttke

2004

Microelectronics Education

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“…The authors are grateful for Dr. M.Blyzniuk and Dr. M.Lobur from Lviv Polytechnic, Lviv, Ukraine for their important contribution in earlier stages of this work described in [8] and [lo].…”

Section: Acknowledgementsmentioning

confidence: 99%

“…In [8] a new approach was introduced for hierarchical defect simulation based on defect preanalysis for components, and using the results of preanalysis in higher level fault simulation. Here, we generalize this approach by introducing a functional fault model as a method for mapping faults from one hierarchical level to another.…”

Section: Introductionmentioning

confidence: 99%

Defect-oriented fault simulation and test generation in digital circuits

Kuźmicz

Pleskacz

Raik

et al.

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

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A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for the higher level fault simulation purposes. In such a way, the functional fault model can be regarded as interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS'85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results.

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Hierarchical defect-oriented fault simulation for digital circuits

Cited by 17 publications

References 10 publications

Reliability-aimed defect/fault characterization of standard cells of VLSI circuits

Reliability-aimed defect/fault characterization of standard cells of VLSI circuits

Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems

Defect-oriented fault simulation and test generation in digital circuits

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