Fault simulation of the asynchronous sequential circuits is more complicated than fault simulation of their synchronous counterparts. It needs to deal with hazards, oscillations and races. The complex gates in the asynchronous circuits are another challenge especially for deductive fault simulation. In this paper a deductive fault simulator for the speed-independent (SI) asynchronous sequential circuits is presented. The implemented deductive fault simulator was tested using the SI benchmark circuits. The experimental results show significant reduction of the computation time and negligible increase of memory requirements.

No abstract

Built-in self-repair (BISR) is widely used to repair embedded memories within system on a chip (SoC) designs to improve their yield. One key component of the BISR circuit responsible for allocating redundancies is the redundancy analysis (RA) algorithm. One of the most important parameters used to evaluate RA algorithms is repair rate (the ratio of the number of the repaired memories to the number of faulty memories). In most BISR designs, redundancies are used on the row/column level. Some approaches target the block-based architecture where both memories and redundancies are divided into several blocks. Thus, allocation can be done on the block level and is more effective in terms of repair rate. These approaches, however, cannot guarantee optimal repair rate. In this paper, we propose a redundancy analysis algorithm for bitoriented memories with block-based redundancy architecture with optimal repair rate. Keywords-embedded memory; built-in redundancy analysis;repair rate; redundancy analysis algorithm.

Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.

The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.K e y w o r d s: