Delay Faults Testing

Abstract

Embedded digital blocks and their interconnections have to be verified by at-speed testing to satisfy the quality and reliability of nowadays System-on-Chips (SoCs). Once a chip is fabricated, it must be tested for pre-specified clock frequency and therefore testing has also to cover speed related faults as well as stuck-at faults. Claim for delay fault testing grows with new technologies. The importance of researching the delay fault testing grows rapidly and obviously the results are published separately for individual problems. The purpose of the chapter is to give an introduction to testing the timing malfunctions in digital circuits. The classification of existing basic and advanced delay fault models is presented with advantages and limitations. The latest test application techniques are described for scan-based synchronous and asynchronous circuits.

Genetic method for compressed skewed-load delay test generation

“…The excitation vector does not need to be shifted-in but it is derived from the initialization vector. The excitation vector for skewedload test is created by one-bit shift of the initialization vector, and for broadside test it is the response of the circuit to the initialization vector [1]. Skewed-load tests seem to be the appropriate low-overhead way to test delay faults in logic cores of SOCs because the test application requires only one storage element per cell in the WBR and scan chain, and extensive core partitioning is not required.…”

“…This additional area overhead is high and therefore usually unacceptable, especially for complex system-on-chips (SOCs). Logic cores of SOCs surrounded by wrappers need wrapper boundary registers (WBRs) also with two memory elements per cell [1].…”

“…TDF assumes an increased delay on the given circuit line which causes the capture of an incorrect value. Two types of faults are considered on every circuit line: slow-to-raise (STR) and slow-to-fall (STF) [1].…”