Hierarchical Test Program Development for Scan Testable Circuits

Abstract

In this paper a novel hierarchical test program development approach is presented for scan testable circuits. We will show how the test program for scan designs can be developed incrementally, in-line with the hierarchical construction ofthesystem netlist, by differentiating between interior and exlerior tests for each model. Furthermore, it will be shown that byintroducing test assembly, such an hierarchical test program development approach is also applicable when nwcros requiring dedicated test procedures are in use. Therefore itprovides an attractive enhancement of the Macro Testing technique.