High-accuracy modelling of ZVS energy loss in advanced power transistors

Abstract

Two simulation approaches for prediction of energy loss in high-voltage power transistors (~600V) operating under ZVS (Zero-Voltage-Switching) and near-ZVS conditions are presented and proved by experiment in this work. The first approach is based on finite-element simulation whereas the second one proposes a new SPICE model. Different from prior works, both models feature COSS hysteresis and related energy loss, thus showing high precision in replicating waveforms and energy loss for real tests in the primary-side of LLC resonant converters. I.

Analysis of Intrinsic Switching Losses in Superjunction MOSFETs Under Zero Voltage Switching

“…E i might not seem so significant for hard-switching conditions, but it can make the difference under soft-switching operation, especially for low and medium load demands, where conduction power losses are lower and switching losses are relevant because of the high-frequency operation. E i is intrinsic to the structure of SJ-MOSFETs, as it is briefly reproduced in Figure 2a-c and explained in detail in the work of [12], where a physical relationship between C OSS hysteresis and E i was demonstrated, elucidating the existence of energy losses during the charge and discharge of C OSS . Holes and electrons (h+ and e-, respectively, in Figure 2), flowing in parallel to the capacitance, originate stucked charges between the pillars that need to be removed through highly resistive paths that may vary among devices.…”

“…The authors of this paper have previously analyzed the C OSS hysteresis and its related switching losses (including E i ) for different dead-times of three generations of SJ-MOSFETs in an LLC resonant converter in the work of [12]. Moreover, they provide a guideline to select SJ-MOSFETs of different manufacturers to improve the efficiency of this converter in a wide power range in the work of [13].…”

Analysis of Large-Signal Output Capacitance of Transistors Using Sawyer–Tower Circuit

“…To elucidate, we consider that the device has reached steady state, where the dc bias in C ref is given in (12), in which V FW is assumed to be a fixed dc voltage drop independent of the level of reverse current.…”

Novel Selection Criteria of Primary Side Transistors for LLC Resonant Converters

“…However, there are many factors to consider when calculating PDR (11) [7] (Figure 5b,c), such as: 3 (7), 4 (8) (losses due to the commercial driver IC itself, commonly disregarded), driving-on (9) and driving-off losses (10).…”

“…As has been shown, PSW losses are significant, especially at low and medium load, even if the converter is working with ZVS. It is important to predict and quantify those additional soft-switching losses, ESW_SOFT [8].…”