High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Zhu, Yufei; Zuo-cheng, Xing; Li, Zerun; Zhang, Yang; Hu, Yifan

doi:10.3390/sym13040700

Cited by 4 publications

(9 citation statements)

References 25 publications

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“…In addition, the LUT and XOR tree structure of 256-bit parallel CRC calculation uses the remaining resources. Although this design is 40% higher than [21] in terms of resource utilization, the proposed encoder is suitable for full-size Z and includes CRC calculation. In [19,21], ASIC synthesis is performed for different lifting sizes, and five and nine encoders are implemented respectively.…”

Section: Evaluation Resultsmentioning

confidence: 99%

“…Although this design is 40% higher than [21] in terms of resource utilization, the proposed encoder is suitable for full-size Z and includes CRC calculation. In [19,21], ASIC synthesis is performed for different lifting sizes, and five and nine encoders are implemented respectively. Thus these encoders can only work under the specified Z size.…”

Section: Evaluation Resultsmentioning

confidence: 99%

“…For Reference [21], when compared with [19], the maximum encoding latency is reduced by 20 clock cycles. Reference [21] implemented nine encoders for distributed lifting sizes of BG1 and BG2, the application specific integrated circuit (ASIC) synthesis for different lifting sizes. Encoders implemented for different lifting sizes have different performance parameters.…”

Section: Discussion and Comparison With Related Workmentioning

confidence: 99%

“…This paper proposes an optimized coding algorithm and hardware scheduling scheme. Compared with [19,21], the flexibility of the coding architecture has been greatly improved, but the coding delay has not reached the minimum. Under the operating frequency of 580 Mhz, the maximum delay is 875 ns and the peak BG1 throughput is 18.51 Gbps.…”

Section: Discussion and Comparison With Related Workmentioning

confidence: 99%

“…In [20], a flexible and high-throughput 5G LDPC encoder was implemented on the compute unified device architecture (CUDA) platform through the scheme proposed in [19], and the throughput of 38-62 Gbps from 1/2 to 8/9 rate was achieved on a single GPU. In [21], an encoder with the advantages of parallel encoding and pipeline operation is proposed; it was synthesized in a 65 nm CMOS technology and the parallelism of this scheme is higher compared with [19]. In [22], a serial-optimized QC-LDPC encoder is proposed, which uses genetic algorithm to optimize the encoding.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Low-Latency QC-LDPC Encoder Design for 5G NR

Tian

Bai

Liu

2021

Sensors

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In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

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Section: Evaluation Resultsmentioning

confidence: 99%

Section: Evaluation Resultsmentioning

confidence: 99%

Section: Discussion and Comparison With Related Workmentioning

confidence: 99%

Section: Discussion and Comparison With Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Latency QC-LDPC Encoder Design for 5G NR

Tian

Bai

Liu

2021

Sensors

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An Efficient Partially Parallel Encoder Suitable for 5G-LDPC Codes

Jia,

Zhang,

Yin

et al. 2024

2024 9th International Conference on Computer and Communication Systems (ICCCS)

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Security-based low-density parity check encoder for 5G communication

Rajangam,

Alagarsamy,

Radhakrishnan

et al. 2024

Bulletin EEI

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The fifth generation (5G) of mobile telecommunication standards is intended to offer better performance and efficiency. One of the most significant difficulties in delivering safe data transfer through the transmission channel in the emerging 5G technology is channel-coding security. This research primarily focused on offering information transmission that is secure in the place of novel assaults such as side-channel attacks. In this research, we present a low-density parity check (LDPC) encoder that is constructed using the multiplicative masking method to overcome side-channel attacks, one of the most significant security concerns for the upcoming 5G system. As a result, it offers greater security, reduced complexity, and higher performance. Power, area, and delay can all be calculated using LDPC codes. Comparing multiplicative masking implemented LDPC encoders to ordinary channel coding techniques in terms of security seen that multiplicative masking implemented LDPC encoders offer more security. The program Xilinx ISE 14.7 can synthesize the analysis. The advantage of multiplicative masking is that it offers a promising level of security through the principle of randomization, which is the foundation of the procedure. According to the analysis, the secured transmission of the data by the proposed multiplicative masking implemented LDPC encoder is increased.

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High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Cited by 4 publications

References 25 publications

Low-Latency QC-LDPC Encoder Design for 5G NR

Low-Latency QC-LDPC Encoder Design for 5G NR

An Efficient Partially Parallel Encoder Suitable for 5G-LDPC Codes

Security-based low-density parity check encoder for 5G communication

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