2015
DOI: 10.1016/j.mee.2015.07.005
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High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

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Cited by 20 publications
(3 citation statements)
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“…Additionally, Hanju Oh et al focused on the fabrication of fully isolated TSVs with an aspect ratio of 23:1, investigated the integration of high-aspect-ratio TSVs within a microfluidic heat sink using various fabrication processes, proposed a 3D system with TSVs embedded within interlayer-microfluidic cooling, and described the fabrication and the electrical characterization of high-aspect-ratio TSVs within a micropin-fin heat sink in detail [ 33 ]. The distilled water, common acting as a coolant, brought about an impact on the electrical performance of TSVs.…”
Section: Influence Of Microfluidic Cooling On Through Silicon Viasmentioning
confidence: 99%
“…Additionally, Hanju Oh et al focused on the fabrication of fully isolated TSVs with an aspect ratio of 23:1, investigated the integration of high-aspect-ratio TSVs within a microfluidic heat sink using various fabrication processes, proposed a 3D system with TSVs embedded within interlayer-microfluidic cooling, and described the fabrication and the electrical characterization of high-aspect-ratio TSVs within a micropin-fin heat sink in detail [ 33 ]. The distilled water, common acting as a coolant, brought about an impact on the electrical performance of TSVs.…”
Section: Influence Of Microfluidic Cooling On Through Silicon Viasmentioning
confidence: 99%
“…Most importantly, the technology of vertical interconnections using through-silicon vias (TSV) has to be mastered. Recent breakthroughs in this field [4][5][6][7] indicate that chip manufacturers are close to achieving this goal. The bonding technology and mechanical stability is another crucial issue [8,9].…”
Section: Introductionmentioning
confidence: 99%
“…In this paper, the first part of the study focuses on a non-copper-plated area at the bottom of large through-silicon-vias (TSVs). The TSV interconnects provide the shortest electrical pathway, lower power consumption, lower noise, smaller form factor, and yield better performance and more functionality in comparison with the conventional chip multi-layers stacking (CMLS) [8,9]. The most common TSV metallization stack is composed of a copper (Cu) diffusion barrier and a seed layer followed by the bottom-up being electroplated [10].…”
Section: Introductionmentioning
confidence: 99%