For the first time, a scalable, low power, deep-submicron TITSONOS (Thin-Film Transistor Silicon-Oxide-NitrideOxide-Silicon) memory cell is described with characteristics rivaling those of single crystal devices (>IO6 cycles, -1.6V window after 10 years on cycled cell at 85C) showing the promise of 3D integration and ultrasmall cell footprints. The ability to .vertically stack device layers enables the current memory density record of -200Mbyte/cm2, set by 90nm NAND, to be surpassed.

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Through-silicon via (TSV) technology is a key enabler for 3-D and 2.5-D integration, which provides low-power and high-bandwidth chip-to-chip communication. During TSV fabrication, over-etching may cause notching at the base of the TSVs, resulting in TSV diameter variations. Endpoint detection (EPD) techniques are critical for controlling TSV diameter, and detecting the endpoint for low open areas presents a serious challenge to process engineers. In this paper, a hybrid partial least squares-support vector machine model for optical emission spectroscopy data are successfully demonstrated for an EPD of low open area TSVs. Accurate EPD results are shown for 120, 80, and 25 µm diameter TSVs. Index Terms-3-D integration, endpoint detection (EPD), optical emission spectroscopy (OES), through-silicon via (TSV).