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Future high performance 3D systems require a systematic co-design of their electrical interconnect network and their heat removal mechanism. This paper presents fine pitch (20µm) and high aspect ratio (18:1) TSVs integrated in a micropin-fin heat sink capable of removing power density of 100W/cm 2 and resulting in junction temperatures below 50 ºC. IntroductionRecent advances in semiconductor technology have led to emergence of memory intensive computing applications, which require significantly larger hardware infrastructure at lower costs to become economically viable. The general trend shows high performance server installation costs to be significantly lower than their running costs, primarily in terms of their energy consumption [1]. Therefore it becomes important to mitigate this gap by developing technologies that are more energy efficient and deliver higher performance at lower energy costs. Three-dimensional IC technology is pursued by many with a promise to solve the above mentioned interconnect problems and to develop energy efficient computing platforms through 3D integration of logic, memory, and optoelectronic devices [2],[3],[4],[5].

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