High current 3D symmetrical inductor integrated in an advanced HR SOI CMOS technology targeting RF power applications

Gianesello, Frédéric; Gloria, D.; Bon, O.; Rauber, B.; Raynaud, C.

doi:10.1109/rfic.2009.5135593

Cited by 6 publications

(2 citation statements)

References 6 publications

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“…Several papers have reported efforts to create highquality inductors in HR-SOI processes since at least the early 2000s [1][2][3][4]. Q values reported vary from the range of 10 to 15, to as high as 30 or more, depending on the inductor's size, number of turns, frequency range, and the thickness of metals available.…”

Section: Previous Workmentioning

confidence: 99%

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

Kuhn

2012

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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Silicon-on-insulator processes have the potential to realize high-quality factors in spiral inductors, but only if the loss mechanisms involved are clearly understood. Partially-depleted SOI (PD-SOI) processes must address losses in the semiconducting Silicon layer below the spiral inductor turns, even when high-resistivity substrates are employed. These losses are illustrated with a simplified lumped-element model and an array of inductors with different materials below is measured to confirm the theory. Q values achieved are up to 19 in the popular frequency range of 1 to 6 GHz without the use of expensive thick-metal in the process.Index Terms -SOI, inductor, quality factor.

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Section: Previous Workmentioning

confidence: 99%

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

Kuhn

2012

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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“…Many proposed technologies focus mainly on passive device loss enhancement. This is the case for approaches that use high resistivity silicon HRS [1], SOI [2] or organic laminates [3] [4]. These technologies provide high-Q passive devices but fail to meet low-cost requirements and often need extra packaging steps for use.…”

Section: Introductionmentioning

confidence: 99%

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

Ghannam

Bourrier

Ourak³

et al. 2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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International audienceThis paper presents a new and efficient low-cost multi-layer 3D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multi-level 3D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer which is patterned underneath specific locations to create the desired 3D interconnect shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3D copper electroplating process is later used to grow 3D interconnects, insuring transition between all metallic layers. Finally, high-Q (55 @ 5 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process

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Layout optimized non-uniform series-parallel inductors for high inductance density and quality factor

Vanukuru

Groves

2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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High current 3D symmetrical inductor integrated in an advanced HR SOI CMOS technology targeting RF power applications

Cited by 6 publications

References 6 publications

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

Loss mechanisms and quality factor improvement for inductors in high-resistivity SOI processes

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

Layout optimized non-uniform series-parallel inductors for high inductance density and quality factor

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