High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

“…However, there has been very little work being done on SRAM array evaluation for cryogenic-specific applications. A 10 nm Fin Field-Effect Transistor (FinFET) technologybased SRAM study shows an increment in the Read Noise Margin (RNM) at 77 K [7]. Apart from noise margin, authors have also reported that a 128 × 128 SRAM array shows a remarkable improvement in the energy-delay product at 77 K compared to 300 K. Although authors in [7] presented a detailed investigation of the SRAM cell down to 77 K, they have not evaluated the impact of different array sizes.…”

“…A 10 nm Fin Field-Effect Transistor (FinFET) technologybased SRAM study shows an increment in the Read Noise Margin (RNM) at 77 K [7]. Apart from noise margin, authors have also reported that a 128 × 128 SRAM array shows a remarkable improvement in the energy-delay product at 77 K compared to 300 K. Although authors in [7] presented a detailed investigation of the SRAM cell down to 77 K, they have not evaluated the impact of different array sizes. Authors in [8] present a detailed study on cryogenic caches and their optimization at the architectural level.…”

“…Furthermore, a large memory is needed to have a fault-tolerant quantum computing system where the Static Random-Access Memory (SRAM) can be employed as a weight element for quantum error correction circuitry [6]. Similarly, the computing cores in high-performance computers continuously access the on-chip SRAM-based cache memories operating at cryogenic temperatures [7]- [9].…”

“…Cryogenic computing promises a significant improvement in the performance and power consumption for quantum computing, exascale and high-performance computing, and deep space electronics (Fig. 1) [1]- [3], [7], [8], [10]- [13]. A lower I leak in CMOS transistors and smaller wire resistance at cryogenic temperatures can help to further upscale the clock frequency of the computers under a constant power budget.…”

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

“…ULTIPLE gate FETs are the most promising devices to succeed planar MOSFETs in advanced technological nodes, allowing for the continuation of scaling [1]. Multiple-gate devices have achieved enough maturity for mass production and can already be found in commercial applications [2], [3], [4]. The reduction of fin height gave origin to nanowire and nanosheet transistors, whose fin height (HFIN) is in the order of 10 nm.…”