High-density chain ferroelectric random-access memory (CFRAM)

Takashima,; Kunishima,; Noguchi,; Takagi,

doi:10.1109/vlsic.1997.623818

Cited by 9 publications

(4 citation statements)

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“…In this case, the current flows some ReRAM cells, then combined resistance can be measured. This architecture reduces the number of Source Lines (SL) and Bit Lines (BL) [14][15]. Then, each of these Lines can be manufactured thicker to suppress the resistance.…”

Section: Hdc and Language Classificationmentioning

confidence: 99%

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3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing

KIHARA,

MATSUI,

TAKEUCHI

2024

IEICE Trans. Electron.

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In this work, we propose a 1T1R ReRAM CiM architecture for Hyperdimensional Computing (HDC). The number of Source Lines and Bit Lines is reduced by introducing memory cells that are connected in series, which is especially advantageous when using a 3D implementation. The results of CiM operations contain errors, but HDC is robust against them, so that even if the XNOR operation has an error of 25%, the inference accuracy remains above 90%.

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Section: Hdc and Language Classificationmentioning

confidence: 99%

“…In addition, cell size is expected to be smaller. According to [14], the chain cell structure reduces the area per cell from 8F 2 to 4F 2 . We assume that a similar effect might be expected with ReRAM.…”

Section: Hdc and Language Classificationmentioning

confidence: 99%

3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing

KIHARA,

MATSUI,

TAKEUCHI

2024

IEICE Trans. Electron.

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“…The phase‐change elements are stacked upon selection transistors, and as a result the area of the memory cell can be reduced to 4F 2 (F: design rule), just as in the case of NAND flash memory, which offers a cost reduction compared to the conventional design. Such a chain structure was previously used in capacitor‐type memory (chain FeRAM [ferroelectric RAM] ) but Ref. was the first to use a chain structure for resistor‐type memory.…”

Section: Introductionmentioning

confidence: 99%

Design Technology of Stacked‐Type Chain PRAM

Kato

Watanabe

2015

Elect Comm in Japan

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SUMMARYA stacked-type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked-type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low-cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked-type chain PRAM is a promising candidate for realizing high-speed and low-power future nonvolatile semiconductor memory. C⃝ 2015 Wiley Periodicals, Inc. Electron Comm Jpn, 98(2): 32-42, 2015; Published online in Wiley Online Library (wileyonlinelibrary.com).

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“…Recently, chain PRAM has been newly proposed for achieving lower bit cost (fabrication cost of one bit) [3]. It adopts the chain structure [4] [5] which connects the parallel connection of a transistor and a PCM connected in series. In [3], this chain structure is fabricated in a horizontal plane (xy plane).…”

Section: Introductionmentioning

confidence: 99%

Analysis of bit cost and performance for stacked type chain PRAM

Kato¹,

Watanabe²

2013

ces

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The analysis of bit cost and the performance of stacked type chain PRAM bas been newly described. Using the optimized number of layer the bit cost of stacked type chain PRAM with stacked horizontal plane structure or BiCS type structure can be reduced compared with that of 1 layer NAND flash memory. The smallest bit cost of BiCS type structure is as small as 0.08 of 1 layer NAND flash memory using the optimized number of layer of 64. The delay time of WL and BL of stacked type chain PRAM with BiCS type structure has been estimated. Using the optimized number layer of 64 for realizing smallest bit cost the delay time of WL and BL are less than 5ns which is competitive to DRAM. Because of estimated high speed characteristics and low bit cost, the chain PRAM wth BiCS type structure is the promising candidate for replacing DRAM and NAND flash memory.

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High-density chain ferroelectric random-access memory (CFRAM)

Cited by 9 publications

References 0 publications

3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing

3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing

Design Technology of Stacked‐Type Chain PRAM

Analysis of bit cost and performance for stacked type chain PRAM

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